DS125DF1610: DS125DF1610

Michael Geng

Part Number: DS125DF1610

Four DS125DF1610 are used in our design. When we use them without funciton of cross point and boardcast, one of it shows CDR unlockded on one channel.

The input data come from FPGA in other borad.

We tested power and input clock， the noise of power and ppm of clock are ok.

The registers value are shown below. Is there any problem with regisrer sets? Why CDR unlocked?

ds125SharedRegDump devid 0
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 08 71 20 00 01 08 00 05 00 00 01 50 00 7a 00 ff
0x10 : ff ds125ChannelRegDump devid 0 channel 0
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 31 8a 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 00 25 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 14 00 0c 3f 3f 00 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 1
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 32 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8d 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 00 68 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 15 00 0c 3f 3f 01 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 2
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 2e 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 07 a9 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 16 00 0c 3f 3f 02 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 3
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 30 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8d 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 02 e4 00 00 00 08 00 00 00 00 00 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 17 00 0c 3f 3f 03 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 4
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 31 84 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8d 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 02 e4 00 00 00 00 00 00 00 00 00 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 14 00 0c 3f 3f 00 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 5
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 34 96 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 07 f5 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 15 00 0c 3f 3f 01 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 6
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 34 8d 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 02 e4 00 00 00 00 00 00 00 00 4f 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 16 00 0c 3f 3f 02 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 7
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 34 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8d 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 07 9e 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 17 00 0c 3f 3f 03 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 8
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 9c 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 33 8d 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 00 7e 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 14 00 0c 3f 3f 00 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 9
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 9c 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 31 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 07 e0 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 15 00 0c 3f 3f 01 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 10
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 33 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 01 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 02 e4 00 00 00 00 00 00 00 00 3a 00 00 02 1c 01
0x90 : 00 00 00 00 00 00 16 00 0c 3f 3f 02 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 11
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 30 84 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8d 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 00 00 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 17 00 0c 3f 3f 03 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 12
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 33 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 00 13 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 14 00 0c 3f 3f 00 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 13
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 35 7e 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 02 e4 00 07 ff 00 00 00 00 07 97 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 15 00 0c 3f 3f 01 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 14
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 35 84 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8e 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 03 e4 00 00 00 00 00 00 00 00 1f 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 16 00 0c 3f 3f 02 d5 99 96 a5
ds125ChannelRegDump devid 0 channel 15
0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 : 00 80 dc 00 01 01 01 01 60 00 10 6f 08 b4 93 69
0x10 : 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e1 55
0x20 : 00 00 00 40 00 00 00 34 87 40 30 0f f2 00 00 b6
0x30 : 00 20 11 88 bf 1f 30 00 10 00 00 33 8d 35 43 c7
0x40 : 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
0x50 : 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
0x60 : 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 80
0x70 : 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a
0x80 : 02 e4 00 00 00 00 00 00 00 00 1c 00 00 02 1c 00
0x90 : 00 00 00 00 00 00 17 00 0c 3f 3f 03 d5 99 96 a5

over 2 years ago

Evan Mayhew over 2 years ago

TI__Mastermind 24998 points

Hi Michael,

Could you clarify how you are observing that CDR is unlocked on some channels? Referencing 0x78[4] for CDR lock status, I see all 16 channels indicate CDR locked (0x78 = 0x30 for all channels).

If possible, please share a register dump when is CDR unlocked so I may troubleshoot further.

Thank you,

Evan

Michael Geng over 2 years ago in reply to Evan Mayhew

Prodigy 40 points

Hi，Evan

Thanks for your replying.

We read 0x02[4] to monitor CDR lock status. The file of ZHCAA42 shows CDR lock status can read by 0x02[4].

We tested functions with scripts. It's very pity that we just have the print message and didn't save register values when CDR unlocked

Is there any problems with the register sets?

Evan Mayhew over 2 years ago in reply to Michael Geng

TI__Mastermind 24998 points

Hi Michael,

Michael Geng said:
When we use them without funciton of cross point and boardcast, one of it shows CDR unlockded on one channel.

I notice that registers 0x9B and 0x96 are modified in each channel to enable crosspoint mode - is that the intended setting?

It seems this register dump may be for the working case with crosspoint enabled. Registers 0x96 and 0x9B should be left at default values if crosspoint is not being used.

Thank you,

Evan

Michael Geng over 2 years ago in reply to Evan Mayhew

Prodigy 40 points

Hi，Evan

Thanks for your checking.

We did not intend use the function of cross point.

But we found if we set 0x96[4] to 0 and 0x96[3:2] to 10, it can not work.

If we set 0x96[4] to 1 and 0x96[3:2] to 10, it can not work normally

Evan Mayhew over 2 years ago in reply to Michael Geng

TI__Mastermind 24998 points

Hi Michael,

In this case, I wonder if the routing of some channels may be swapped and will only work during crosspoint mode. Are you able to share a schematic and block diagram with the intended connections from the retimer to FPGA?

Thank you,

Evan

Michael Geng over 2 years ago in reply to Evan Mayhew

Prodigy 40 points

Hi, Evan

This is our test data path.

We use retimer channel direactly, for example, RX of channel 0 connect to TX of channel0.

In this situation, What values should be set of 0x96 and 0x9B?

Thanks!

Evan Mayhew over 2 years ago in reply to Michael Geng

TI__Mastermind 24998 points

Hi Michael,

If each channel has an independent signal directly routed from RX0->TX0, RX1->TX1, ... , then registers 0x96 and 0x9B should be left at default values.

If you leave these registers at default, but toggle 0x96[3] to 1, does the behavior you are seeing change?

Thank you,

Evan

Michael Geng over 2 years ago in reply to Evan Mayhew

Prodigy 40 points

Hi，Even

As we communiated befor,we read 0x02[4] to monitor CDR lock status. The file of ZHCAA42 shows CDR lock status can read by 0x02[4]。

Is it ok? Or we should read 0x78[1]

Michael Geng over 2 years ago in reply to Evan Mayhew

Prodigy 40 points

Hi,Evan

The default values of 0x96 and 0x9B are 4 and 0.

I checked Figure 3 on datasheet, which is cross point switch diagram. It shows data bus, which controlled by register of 0x96[1:0], and control bus, which controlled by 0x9B[1:0] should be set. For example, if QUAD 0 of CHB RX to CHB TX, set 0xFC[1] to 1, 0x96[1:0] to 01, 0x9B[1:0] to 01.

If leave 0x96 and 0x9B at default, I think the channels won't work except CHA.

Evan Mayhew over 2 years ago in reply to Michael Geng

TI__Mastermind 24998 points

Hi Michael,

0x78[4] and 0x02[4] are both valid bits to reference for CDR lock status.

Michael Geng said:
For example, if QUAD 0 of CHB RX to CHB TX, set 0xFC[1] to 1, 0x96[1:0] to 01, 0x9B[1:0] to 01.

Can you clarify how you found this configuration for CHB RX -> CHB TX? This does not follow my understanding of cross-point mode.

Please share a register dump and test results while 0x9B and 0x96 are left at the default values. This configuration is expected to work if signals are routed directly from each input to output (RX0->TX0, RX1->TX1, ...) .

Thank you,

Evan

Michael Geng over 2 years ago in reply to Evan Mayhew

Prodigy 40 points

Hi, Evan

As it shows in the picture, 0x96[1:0] choose data bus, 0x9B[1:0] choose control bus. If signals are routed directly, for example CHB RX -> CHB TX, we think 0x96[1:0] and 0x9B[1:0] should be set to 01.

We will test the situation that 0x9B and 0x96 are left at the default values and give you feedback.

Thanks very much!

Evan Mayhew over 2 years ago in reply to Michael Geng

TI__Mastermind 24998 points

Hi Michael,

0x96[1:0] and 0x9B[1:0] allow you flexibility over which channel's signal detect / EQ control to choose from for the selected channel output, assuming there is some cross-point switching intended.

For example, if you are writing to channel register C with cross-point enabled, and set 0x96[1:0] and 0x9B[1:0] to 01, then the signal chain becomes:

RX(B) -> CTLE (B) -> Multi-Point Buffer (B) -> TX(C)

These registers do not need to be modified if cross-point mode is not intended.

Thanks for performing tests at default values.

Regards,

Evan

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DS125DF1610: DS125DF1610