TL16C752C: Phenomenon where the value of register IER does not change from the initial value.

Hi Conor,

I am looking into this question in more detail. I will get a response to you before noon CST tomorrow. 

So far in Q1, the order of code looks to be correct, and the 1ms delays are more than enough time for the address hold time, data hold time, data setup time, and IOW strobe width. All of those values are in the ns range, so 1ms is more than enough. 

I will double check register setting in Q2 tomorrow, and get answers for Q3-Q5 aswell. 

Regards,

Tyler

Hi Conor,

Conor said:

Q1.
I tried to change the value of register IER based on the timing chart in the data sheet, but the value read out was not changed from the initial value. Please check if the method of changing register IER is correct.

1. set RESET = Low->Hi->Low to initialise. 2.
2. set IOW = Hi. 3.
3. delay (approx. 1 ms).
4. set A[2:0] = 001.
5. delay (approx. 1 ms)
6. Set CSA = Lo. 7.
7. delay (approx. 1 ms)
8. Set IOW = Lo.
9. delay (approx. 1 ms)
10. set D[7:0] = 0000 0001.
11. delay (approx. 1 ms)
12.Set IOW = Hi.
13. delay (approx. 1 ms)
14.Set CSA = Hi.
15. delay (approx. 1 ms)
※The delay (approx. 1 ms) is calculated from the clock 19.6608 MHz and obtained by the following process.
----
for(i = 0; i < 5; i++)
{
NOP();
}
----

I am assuming you are using the diagram for writing data to the device using figure 1 in the datasheet.

Based upon your sequence of events and the order present in figure 1, this looks correct. What is the value of LCR[7] at the time of writing to IER? 

The whole point of your first part of code is to set the RX data available interrupt correct? 

Conor said:

Q2.
Please check whether the register settings are correct for the specification.
Specification.
　Input clock: 19.6608 MHz
　Baud rate: 2400 bps
　Data length: 8 bits
　Parity check: none
　Stop bit: 1

Register settings
　DLL = 0000 0000
　DLH = 0000 0010
　LCR = 0000 0011
　LSR = 0110 0001
　FCR = 0000 1001
　MCR = 0000 0100
　IER = 0000 0001

Baud = XTAL / (16*Div) = 19.6608MHz / (16 * 512) = 2400 baud

LCR[1:0] = 11 = word length = 8 bits

LSR denotes that transmitter hold and shift registers are empty, THR = empty. 

FCR is set so that transmit and receive FIFO's are enabled. DMA mode 1 selected.

MCR enables the FIFORdy register in loopback controls MSR[6]

IER only turns on the RHR interrupt. THR is disabled along with the other interrupts for receiver line status, modem status, Xoff interrupt, /RTS interrupt, and /CTS interrupt. 

Everything here checks out I believe.

Conor said:

Q3.
Are values not stored in the RHR or RX FIFO for communication to the RXA unless there is a start bit, parity bit or stop bit?

Values should be stored in the RHR 64-byte FIFO when communication occurs on RXA. I am trying to understand Q3 further, but I thought it was standard UART practice to include start/parity/stop bits in each transaction.

Conor said:

Q4.
Is the value not saved in the RHR or RX FIFO unless the data bit between the start bit and parity bit is between 5 and 8 bits? Also, what happens if noise is mixed in the data bits?

I would assume so since the word length is configured in your setup to 8-bits. Therefore, when the RHR is storing information, it will look for the start bit, 8-bit, parity, stop bit format always. For example, if there are only 7 bits of data when configured for 8, then I could see the UART device corrupting that data. 

I am hoping that given a slow baud rate, there is not much noise mixed in the signal. UART attempts to read the data about 50% through the data bit, which allows the data to settle from overshoots/undershoots before sampling the data increasing the robustness of UART. THis is also the reason for parity in case one bit gets flipped in data communication (for 1 parity error). 

If you are concerned about noise, it might be worth gathering a scope capture to analyze the signal shape. 

Conor said:

Q5.
I understand that when the RHR is read out, the RHR is overwritten by the next data stored in the RX FIFO.
For example, if there is data that is wanted one after the other, the RHR value is read out once and then the RHR is read out again. Is my understanding correct?

This would make sense since this is exactly what a FIFO (First in first out) does. RSR (receiver shift register) shifts data serially from the RXA pin converting it to parallel data before moving it into the RHR. When reading the RHR, the first byte of data that was put into the register, is the first byte of data that will be read from the register. Data is read on the D0-D7 pins, once the RHR is read again, this data is overwritten by the next byte in line. 

Regards,

Tyler

Hi Tyler,

Thank you for your reply. We will refer to it as we proceed with our development work.

Tyler Townsend said:

Based upon your sequence of events and the order present in figure 1, this looks correct. What is the value of LCR[7] at the time of writing to IER? 

Writing to IER with LCR[7] = 0. I read the LCR before writing to make sure LCR[7] = 0.

Thanks,

Conor

Hi Conor,

Thanks for the information. Looking forward to hear feedback from your work.

Regards,

Tyler