TUSB1210: DESIGN REVIEW AND CLOCK LEVEL TRANSLATOR

Hi,

We are using TUSB1210BRHBR for USB to ULPI interface. Kindly provide your suggestions for the below questions.

1.We are performing for Host, device and Host OTG configurations, as in host configuration we are providing board supply of 5V to load switch, if the jumper J108 is shorted the board supply 5V to provided to VBUS pin of the transceiver. In case of device configuration, we are providing the 5Vsupply from the USB 2.0 Micro B connector to the VBUS pin of the transceiver. Kindly review the design for these configurations and share your feedback.

2.Can we use USB 2.0 Micro B connector for these applications or we need to use 2.0 Micro AB connector.

3.And also for REFCLK we are providing the clock of 26MHZ from both external oscillator and FPGA in a tripad connection. FPGA used in our design has voltage level of 1.8V, but for REFCLK input the amplitude of the clock signal needs to be from 3V to 3.6V as mentioned in datasheet. Please suggest a possible level translator 

Thanks

S Sathya shree