DS90UB948-Q1: 948 chip not found on host side

Hey Cherry,

Thanks for the request. I will review and get back to you by Friday Aug, 11th. 

Regards,
Fadi A.

Hey Cherry,

I don't see an issue with schematic. Seems like it's setup for STP 5 mbps backchannel dual OLDI output. 

In order to further help you would need to be able to reproduce the issue on bench, and we would need a register dump of a good vs. bad run as a starting point. 

Regards,
Fadi A.

Hello Fadi A,

Thank you for the support.

Fadi Abdulhameed said:

In order to further help you would need to be able to reproduce the issue on bench,

They're trying to reproduce.

Also, the 948 chip LVDS input signal has waveforms when tested using an oscilloscope, the chip power is good, PDB is high, but the lock signal is always low. Would it be possible to figure out from the input signal waveform captured on the oscilloscope is the PLL out of lock due to clock instability? Or based on the above response, what other causes may cause the PLL to lose lock besides the possibility that an input clock instability?

Does the PLL unlock status affect both image display and transmitted I2C communication? Or is the lock/unlock primarily a video signal based clock stable? 

Thanks and regards,

Cherry

Hey Cherry,

Cherry Zhou said:

Does the PLL unlock status affect both image display and transmitted I2C communication? Or is the lock/unlock primarily a video signal based clock stable? 

If you have I2C issue that could be an issue with forward channel or back channel. But if you don't have video that's only a forward channel issue. Your lock status by default will check for active video, see register 0x34 on Des side. 

You could try running patgen testing from 941AS to see if you get lock on 948 as a first step. Then you can try different timing configuration to narrow down where the issue is coming from. 

941AS can generate internal timing and CLK and can do a different combination of timing/clk modes - This helps isolate whether the issue is with timing or CLK or whether it's coming from the input side (video/clk source) or whether it's coming from the 929 itself. 

1- Internal - Everything will be internally generated; HS, VS, DE, CLK and Video (if no issue is observed then the issue is likely coming from the video source)

2- Internal w/ext clk is HS, VS, DE and Video are generated internally but using External PCLK (if you see an issue in this mode, this point to an external CLK issue from the source) 

3-  External is HS, VS, DE and CLK are generated externally (if you see an issue in this mode, this point to an external CLK/timing issue from the source) 

Next, you need to choose Timing Source - choose timing based on the 3 modes mentioned above and then for spec you could choose the resolution you need for your display, or can customized your own. You could run fixed pattern or you could select Color Bars or if you choose to do fixed patterns and could enable scrolling to go through multiple patterns, so whichever method you want. Then finally, you could Enable Generator to start sending the Patgen with the setting you have configured. 

Regards,
Fadi A.