DP83867IR: High rise time and fall time on GTX

Ankit Nikumbh

Part Number: DP83867IR

Hi,

We are using DP83867IR PHY in RGMII mode for one of our custom board design with AM6254 SoC. Here I have attached schematic connection diagram between SoC and PHY chip.

As per PHY datasheet rise and fall time value on GTX should be max 0.75ns (20% to 80%) but we are observing higher rise and fall time than that. We have kept default 33ohm series resisters as well to tune whenever required.

With 33ohm series resistor, we are getting around 1.6ns and 1.4ns as rise and fall time respectively. So we have tuned the series resistors by making it 0ohm directly. And we are getting updated times as 1.17ns and 1.13ns respectively which is still more than defined value in datasheet.

So, is there any other way/aspect to reduce rise and fall time by changing in HW? Or any changes in SW code which we might have missed?

Here I have attached waveforms captured on TXC signals and measured rise and fall time between 20% - 80%.

Regards

Ankit N

over 2 years ago

Hillman Lin over 2 years ago

TI__Mastermind 25945 points

Hi Ankit,

May I ask what is the length of the RGMII traces? Is your total length of each of your RGMII traces less than 6 inches or 6000mils?

Could you also check the trace width and make sure it is impedance matching with 50ohms?

Could you also provide a layout snapshot?

Regards,

Hillman Lin

Ankit Nikumbh over 2 years ago in reply to Hillman Lin

Prodigy 80 points

Hi Hillman,

Thank you for your response.

Yes all RGMII traces are less than 6 inches. Trace width is around 5.2mils and it is matching with 50ohm impedance. Attaching layout snapshot FYR.

Let me check register 0x0170 bit [4:0] setting from SW team. Is there any table which shows 00000...11111 configuration?

Regards

Ankit N

Hillman Lin over 2 years ago in reply to Ankit Nikumbh

TI__Mastermind 25945 points

Hi Ankit,

Are you facing a functionality issue with this waveform?

May I ask which position did you probe the signal? receiver side (RX) or transmitter side (TX)?

Regards,

Hillman Lin

Ankit Nikumbh over 2 years ago in reply to Hillman Lin

Prodigy 80 points

Hi Hillman,

No, we are not facing any functionality issue. We are just validating our design as per our EDVT test plans.

We are probing the signals at receiver(i.e. at PHY pins) side. We are probing at the right place right?

Regards,

Ankit N

Hillman Lin over 2 years ago in reply to Ankit Nikumbh

TI__Mastermind 25945 points

Hi Ankit,

Just want to double check, if you are probing on the TX_CLK signal (receiver side of the PHY)?

If so, could you also probe it near MAC side and see is there any difference between the probe position?

Thank you,

Hillman Lin

Ankit Nikumbh over 2 years ago in reply to Hillman Lin

Prodigy 80 points

Hi Hillman,

Yes I am probing on the TX_CLK signal (receiver side of the PHY).

Let me try to probe on MAC(SoC side) and will get back to you.

Regards

Ankit N

Hillman Lin over 2 years ago in reply to Ankit Nikumbh

TI__Mastermind 25945 points

Hi Ankit,

Sure, let me know if you have more finding.

--
Regards,

Hillman Lin

Ankit Nikumbh over 2 years ago in reply to Hillman Lin

Prodigy 80 points

Hi Hillman,

No success at the MAC side also. Getting same results on MAC.

Let me know any other steps if you have. Can we able to set/increase drive strength of signals? if yes then how can I do please let me know.

Regards,

Ankit N

Hillman Lin over 2 years ago in reply to Ankit Nikumbh

TI__Mastermind 25945 points

Hi Ankit,

Are you seeing the similar waveform on the MAC side as well? If so, it seems like the MAC is outputting distorted clock signal to the PHY. Is there a way to increase the drive strength from the MAC side?

--
Regards,

Hillman Lin

Ankit Nikumbh over 2 years ago in reply to Hillman Lin

Prodigy 80 points

Hi Hillman,

From hardware side earlier we have kept 33ohm series resistor and in current setup it is made to 0ohm and still we are getting high rise and fall time. So think from Hardware side it is not possible, right?

From software side any possibility to increase drive strength for the RGMII signals? if yes, please let me know the steps to change in code for the same.

Regards

Ankit N

Hillman Lin over 2 years ago in reply to Ankit Nikumbh

TI__Mastermind 25945 points

Hi Ankit,

Yes, I agree with you it might be on the software side. However, I do think might be the MAC side instead of the PHY side that need to increase the drive strength. Since TX_CLK is the output of the MAC and input of the PHY in RGMII interface. That is why I am asking is it possible to increase the drive strength on the MAC side? PHY does not have much control since it is the input side or receiver side for TX_CLK pin.

Sincerely,

Hillman Lin

Interface

Interface forum

DP83867IR: High rise time and fall time on GTX