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PCA9534: Silicon and Documentation Issue

Garrett Gustafson
Prodigy 10 points
Part Number: PCA9534

Hello Ti,

Hopefully this is a suitable place for this report.

We have discovered what we believe to be a silicon issue with at least more recently Fabricated PCA9534 parts. 

The polarity inversion register (register 2) should be initialized as 0x00 on startup however we have observed that on some chips this is not the case and one or more bits in this register may be initialized as a 1.

A suitable workaround for this issue appears to be to write the default values to the register via I2C at startup.

There is also a documentation issue in the datasheet:

"The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained."

In practice, the polarity inversion applies to the entire Input register and is not affected by the whether the bit is set as an output or input in the configuration register.

We have been using this part in our design for ~10 years, but have only recently received field reports and reproduced this issue in our lab. Here are the markings of a sample that has exhibited the issue: PD534 TI 13K AN89.

If you have any questions please let us know and we're happy to answer if we can.

-Garrett

 

  • 0
    Guru 317280 points

    The bits in the Polarity Inversion register affect all port reads (see the XOR gate in figure 9-2). The description "of pins defined as inputs" is not strictly correct because it is possible to also read pins that are configured as outputs.

    PCN 20210315001.1 introduced devices with a new die. But the datasheet limits did not change. Are there glitches on the power supply? Does the supply conform to the limits in table 11-1?

  • 0
    Prodigy 10 points

    Hello Clemens,

    All in agreement on the documentation note.

    The only thing I could point to on 11-1 is that our fall rate when powering down can exceed 100mS. Is it even possible that there would be a memory effect of how the chip was powered down many seconds before?

    -Garrett

  • 0 in reply to Garrett Gustafson
    Guru 317280 points

    No, that would not affect powering up.

  • 0 in reply to Garrett Gustafson
    TI__Mastermind 48128 points

    Hi Garrett,

    I ran the part number, and was able to trace it back to one of our facilities, so we are good on that end knowing that the device is not possibly counterfeit. 

    The 100 ms fall rate shouldn't effect the powering up of the device. 

    Is this error occurring on all devices, or is the failure sporadic? 

    Do you have a schematic and or/scope capture showing the issue of the error? 

    Regards,

    Tyler