DP83TC813R-Q1: spec clarifications

Hi O'Mellin

Why does the customer require the specs listed in (1) and (2)? Is there some problem with the PHY?

1. RGMII RX[3:0]: Vout_H and Vout_L

                TX[3:0]: Vin_H and Vin_L

The VIH and VIL levels are the same as the VIH and VIL levels mentioned in section 7.5 in the IO characteristics section.

2. MDI output common mode voltage: Vout_H and Vout_L

 The common mode voltage is not characterized.

        3. How to understand T5.2? what is the delay offset for all supplies?

This means that if all the supplies do not ramp at the same time, they all must ramp within 10 ms of each other.

4. How to capture T5.6? Is there a sign or mark that shows strap latch-in occurs? I want to measure T5.6

Why do you want to measure this value? T5.6 is ensured by the PHY's design, you just need to follow PHY power up and design requirements.

5. T5.7 means which CLKOUT for DP83TC813R?

This refers to the CLKOUT pin.

5. Is there a sign or mark for idle stream start-up?  Can I capture the sign or mark to measure T5.6?

You can measure the idle stream by measuring the MDI signal. You can see the idle stream waveform in section 9.2.3 of the datasheet. Again, T5.6 is ensured by the PHY.

Best regards,

Melissa

Hello, Mellisa

thanks for your answer. here below is my reply:

you asked many whys: I am working on the test, so more details about the para., the better.

Q1: clear

Q2: MDI output common mode voltage: Vout_H and Vout_L

       The common mode voltage is not characterized.

       Are any standards available for definition of MDI common voltage referring to GND and its measurement? from IEEE 802 or OPEN Alliance??

       why no common voltage exists for 100base-T1? automotive CAN bus is also differential type, but common voltage also matters a lot..

Q3: How to understand T5.2? what is the delay offset for all supplies?

       This means that if all the supplies do not ramp at the same time, they all must ramp within 10 ms of each other.

       Could you give a timing figure?  the figure in datasheet is not easy to understand.

Q4: is T5.6 available for measurement outside ethernet IC? and how?

Q5: is the clock this pin for DP83TC813R-Q1?

Q6: clear.

Hello, Melissa

It is the fundamental unit test that I am performing on the PHY IC. It is 100base-T1 with RGMII. The basic timing and voltage are necessary to record as raw data in case of future review and re-check.

of course, the automotive ethernet standards from IEEE and OPEN Alliance are respected. I raised the questions based on my experience and intuition.

Q2: MDI output common mode voltage: Vout_H and Vout_L

Thank you, Melissa.

all questions are clear, except Q4: is T5.6 available for measurement outside ethernet IC? and how?

It is feasible. As previously mentioned, the way to measure T5.6 is to probe RESET and a strap pin. Then, hold the PHY in RESET and T5.6 will be the time from when RESET finishes toggling and the strap pin latches into the correct state. 

is there a sign for the behavior that the strap pin latches into the input voltage?

CH1 & CH2 are power supplies, and CH3 is reset signal.

CH4 is the strap pin voltage (mode 2 in 2-levels configuration). during the high duration, which moment is the voltage latched in?

Hi Yanan, 

The time you have measured in the diagram should be the latch-in time. You can also try holding down reset a few seconds after power up to confirm you get similar results. 

Best regards,

Melissa

Thank you.. Melissa.

I have another question about the starting-up timing of oscillation after power-up.

I snapped the waveform below:

1. Ta=25°C, 

CH1 & CH2 : power supplies;  CH3: reset;  CH4: CLKOUT.  from reset released to CLKOUT starting switching: 7.58ms

CH1: VDDA;  CH2: XI;  CH3: XO;  from reset released to crystal oscillating stable(XI pin): 3.87ms

                                                       from reset released to crystal oscillating stable(XO pin): 3.63ms

2.  Ta=85°C, 

CH1 & CH2 : power supplies;  CH3: reset;  CH4: CLKOUT.  from reset released to CLKOUT starting switching: 7.58ms

CH1: VDDA;  CH2: XI;  CH3: XO;  from reset released to crystal oscillating stable(XI pin): 49.7ms

                                                       from reset released to crystal oscillating stable(XO pin): 19.6ms

3.  Ta=-40°C, 

CH1 & CH2 : power supplies;  CH3: reset;  CH4: CLKOUT.  from reset released to CLKOUT starting switching: 7.22ms

CH1: VDDA;  CH2: XI;  CH3: XO;  from reset released to crystal oscillating stable(XI pin): 27.7ms

                                                       from reset released to crystal oscillating stable(XO pin): 13.7ms

question here:

the starting time of XI/XO after power-up @different temperatures differs a lot, but the CLKOUT timing is almost the same. 

1. I think CLKOUT comes from XI/XO, so CLKOUT should be started later than XI/XO. BUT the test result shows opposite result for -40 & 85°C.

I did -40 & 85°C test in thermal chamber, while the 25°C test on the table in the open air. do you think the XI/XO test result is not right? because the oscillator probe has a parasitic capacitance of <12.0pF, which affects the starting up timing a lot with the load capacitance is 8.2pF. should I take CLKOUT timing as XI/XO test result?

2. the XI starting up time is 0.35ms typically.so does the probe capacitance affect the result so much?

3. how should I measure the accurate XI/XO starting time?

Hi Yanan,

Are you seeing any issues or delays with the PHY startup? This would help me narrow down the issue. 

Yanan Xu said:

1. I think CLKOUT comes from XI/XO, so CLKOUT should be started later than XI/XO. BUT the test result shows opposite result for -40 & 85°C.

I did -40 & 85°C test in thermal chamber, while the 25°C test on the table in the open air. do you think the XI/XO test result is not right? because the oscillator probe has a parasitic capacitance of <12.0pF, which affects the starting up timing a lot with the load capacitance is 8.2pF. should I take CLKOUT timing as XI/XO test result?

You are correct that CLK_OUT is based off of XI/XO. XI/XO should be coming up before CLK_OUT. The delays may be caused by the method of measurement. 

Yanan Xu said:

2. the XI starting up time is 0.35ms typically.so does the probe capacitance affect the result so much?

It is possible that the probes and the way you are measuring the CLK signal affects the delay. Note that 0.35 ms is only the typical startup time and that it can go on for longer. 

Yanan Xu said:

3. how should I measure the accurate XI/XO starting time?

You could try adjusting the scope settings (bandwidth limit, acquisition mode, intensity or try out different probes. How are you measuring the signals, could you provide a picture? I might be able to better instruct you with some more context. 

Best regards,

Melissa

Thank you, Melissa

here below is my reply:

Melissa Chang said:

Yanan Xu said:

2. the XI starting up time is 0.35ms typically.so does the probe capacitance affect the result so much?

It is possible that the probes and the way you are measuring the CLK signal affects the delay. Note that 0.35 ms is only the typical startup time and that it can go on for longer. 

the longer startup time is 7.22~7.58ms, which is far more than the typ. 0.35ms..  the deviation is about 20 times the typical value..  is it acceptable for normal operation of IC?

Melissa Chang said:

Yanan Xu said:

3. how should I measure the accurate XI/XO starting time?

You could try adjusting the scope settings (bandwidth limit, acquisition mode, intensity or try out different probes. How are you measuring the signals, could you provide a picture? I might be able to better instruct you with some more context. 

the original setup has been disconnected for other test. so I took some pictures with the same test wire and probe, as below:

the Tek OSC probe: 200MHz BW, 10MΩ, <12pF

Hi Yanan,

Yanan Xu said:

the longer startup time is 7.22~7.58ms, which is far more than the typ. 0.35ms..  the deviation is about 20 times the typical value..  is it acceptable for normal operation of IC?

As long as you don't see any other issues with functionality, this is ok. Does your system have a fast startup time requirement?

Yanan Xu said:

  

I'm guessing the white wire is XI, is this correct? Have you tried probing directly at the pin? How are you probing the power?

I did a very rough measurement with our EVMs with  <1pF, 1MOhm, <=1.5GHz probes, I am seeing a ~3 ms delay. 

Best regards.

Melissa

Hello, Melissa

Melissa Chang said:

Hi Yanan,

Yanan Xu said:

the longer startup time is 7.22~7.58ms, which is far more than the typ. 0.35ms..  the deviation is about 20 times the typical value..  is it acceptable for normal operation of IC?

As long as you don't see any other issues with functionality, this is ok. Does your system have a fast startup time requirement?

I need to confirm the startup requirement..  for now, the ethernet link runs well.

Melissa Chang said:

Yanan Xu said:

  

I'm guessing the white wire is XI, is this correct? Have you tried probing directly at the pin? How are you probing the power?

I did a very rough measurement with our EVMs with  <1pF, 1MOhm, <=1.5GHz probes, I am seeing a ~3 ms delay. 

the white wire is XO, and the XO test setup above is used for -40 & 85ºC.  XO probing for 25ºC is below, with a spiral grounding ring:

the power probing is of this kind below, with leading wire soldered on the input capacitor of the power:

also, could you share your waveforms snapped?

Hello, Melissa

Thanks for your advice. I tried it as below:

Melissa Chang said:

Yanan Xu said:

I need to confirm the startup requirement..  for now, the ethernet link runs well.

As long as your Ethernet PHY is functional and all your system requirements are met, you should not need to worry about a longer XI startup time. 

It looks like you are using the tip and barrel method with a small loop, am I correct? That is good. However, try probing the points closer to the pins and using a probe with a smaller capacitance. 

@room temperature, I used another probe with lower capacitance (3.9pF), and found the startup time is reduced a lot, as below pictures:

CH1: VDDA;   CH2: XI;   CH3: XO     

XI startup time decreased to 2.755ms(3.9pF probe) from 3.87ms (<12pF probe);

XO startup time decreased to 2.295ms(3.9pF probe) from 3.63ms (<12pF probe).

but XI and XO is powered by VDDIO(1.8V), not VDDA(3.3V), so I redo the test with the moment of VDDIO getting ready as timing reference.

@room temperature, waveforms as below:

XI startup time ---- 1.547ms (3.9pF probe);

XO startup time ---- 1.103ms (3.9pF probe).

your test result is about 1.0ms, using a probe with less capacitance than mine. so it is reasonable for your better result.

with the probe capacitance, the XI startup time is 1.547ms, about 4.4 times the typ. 0.35ms, so I think the startup time will be less for the actual circuit without probe involved in the circuit, which should be close to your result 1.0ms.

I will measure the value @ -40 & 85ºC, to check the difference among different temperatures.

                    CH1: VDDIO;    CH2:XI                                                                      CH1: VDDIO;    CH2:XO

also, I have a doubt: why your XI comes to the maximum Vpp (about 1.7V) after only 1 cycle, while mine increases to its Vpp_max gradually in lots of cycles? Below is my schematic. any difference from your EVM circuit?

Hello, Melissa

1.  yes, I agree with you. the higher capacitance leads to higher startup time.

the actual startup time can not be snapped owing to the parasitic capacitance of the OSC probe. instead, a probe with lowest capacitance we can get could and shall be used to take this measurement, to get the nearest data from the actual..

2  I checked the EVM SCH. It also uses passive external crystal oscillator. with my PCBA,  I reproduced your waveform showing a wrong frequency and no gradual change of Vpp, as below:

CH1: VDDIO;  CH2: XI--25MHz clock acquired with a 500kS/s OSC

a high-frequency signal but acquired by a low-sample rate OSC, will lead to the distorted waveform..  25MHz is taken as about 465Hz.

3.  for  -40 & 85ºC, because PCBA is placed in a thermal chamber,  I used a soldered shielded coaxial cable to lead the signal outside the chamber to the OSC. the cable will lead to the extensive startup time a lot, owing to the parasitic capacitance of the cable.

so I redo the measurement @25ºC with the soldered cable, as below comparison. the introduced capacitance of cable matters a lot..

            VDDIO to XI:  1.521ms(25℃--direct probing)                 VDDIO to XI:  4.531ms(25℃--probing with a long wire soldered for XI only)  

Thank you, Melissa.

sure to close the topic.  I will continue to confirm the startup requirement. it is likely to be fine...

nice talking with you..