does the 947 pattern CDIV_N have a range of 2~63 when using 800Mhz clock?
Table 3-9. Pattern Generator Clock Divider N Configuration (PGCDC1)
| Bit | Access | Field | Default (bin) | Description |
| 7:6 | Reserved | 00 | Reserved. Reads return 0, writes are ignored. | |
| 5:0 | RW | PATGEN_CDIV_N | 001000 | Clock Divider: This field configures the "N" clock divider for the internal 200 MHz clock when the pattern generator uses internal timing. Valid values are 2 through 63; values 0 and 1 are reserved and must not be used |
If N range is 2~63? no mater the base clock is 200Mhz or 800Mhz?
