DS90UH925AQ-Q1: dout before PDB and PCLK ?

Hi Oliver,

This power sequence does not look right.

Can you share the schematic?

Best Regards,

Gil Abarca

Hello Gil, as customer is back from break. can you please elaborate on what you find is wrong in regards to power supply sequencing ? in the capture the only power is VDD and it comes first 

thanks 

Gil Additionally here is the scheamtic, but please clarify the above alsoser 925.pdf

Hello Oliver,

Gil is OoO, but Jack will get back to you soon.

Hi Olivier,

Is there a reason for the PCLK pulse? There shouldn't be any inputs driven while power supplies haven't stabilized. But this isn't most likely why DOUT is driven before PCLK and PDB.

The PLL can pick up noise and output this before locking onto the proper data. Is this observation being connected to an issue with the system?

Best,

Jack

Jack, 8just receive the additional info below from customer

The RCAR output is settled as pull up at the init so it's the reason for the first PCLK pulse.

We didn't observe any issue with the system.

As it's not conform to the expectation (datasheet), we want from you to be sure that no potential future issue can arrive.

>> does it help explain why dout is driven so early ?

Hi Oliver,

Just to clarify, is the serializer able to lock with the deserializer and there can be I2C commuincation? Can the customer generate PATGEN?

Best Regards,

Gil Abarca

Gil, system apparently works as it should. valeo is just worried that it doesnt seem to match datasheet and it cant be explained.

so lock and i2c : yes. patgen : yes also, but I guess this would be most interesting if response to previous was a no.

I dont know if they get a lock on the suspicious Dout ( prior to pclk ) , but they do after.

Hi Oliver,

I want to make sure that the signal is noise like Jack mentioned previously. Can you try grounding all the input signals or analyze the DOUT signal before the PCLK is applied?

Best Regards,

Gil Abarca