SN65DSI86: Whether the resolution exceeds 6G can also be supported

user5883945

Part Number: SN65DSI86

Dears,

The maximum MIPI input rate of this conversion IC is 1.5Gbps/lane, and there is only one set of MIPI on my platform. so the conversion chip input is only connected to one set of MIPI, then the maximum is 6Gbps. If my screen resolution is calculated to exceed 6Gbps, can it be driven? Is this input limited? Or only the output eDP side to meet the rate can be (even if it exceeds the conversion IC input rate), the IC does not have an internal buffer, the output can drive a greater rate than the input?

2560* 1600,60 Hz, 24bpp screen, input as long as a group of mipi, can drive?

over 2 years ago

0 Allison Noe over 2 years ago

TI__Intellectual 1265 points

Hello,

DSI86 can support eDP data rates of 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2) per DP lane. What is the DSI pixel clock frequency and eDP data rate you are using? You can reference the DSI86 programming guide to see if the display is supported: https://www.ti.com/lit/an/slla425/slla425.pdf.

Thanks, Allison

0 user5883945 over 2 years ago in reply to Allison Noe

Expert 1806 points

Hi Allison,

After a general calculation, the maximum single-channel mipi is 6Gbps, which supports less than 2560×1600@60Hz, 24bpp, but the mipi output of our platform supports DSC compression. Would you like to ask whether DSI86 can support DSC compressed data transmission?

0 Allison Noe over 2 years ago in reply to user5883945

TI__Intellectual 1265 points

Hello,

The DSI86 does not support DSC Compression. It only supports both non-burst and burst mode packet transmission.

What is the display pixel clock frequency and eDP data rate you are using?

Thanks, Allison

0 user5883945 over 2 years ago in reply to Allison Noe

Expert 1806 points

Hi Allison,

Pixel clock is about 300M, eDP works in HBR mode 2.16Gbps

0 Allison Noe over 2 years ago in reply to user5883945

TI__Intellectual 1265 points

Hello,

Looking at the calculations in the DSI86 programming guide, please note the below:

Stream bit rate = pixel clock x bpp = 300MHz x 24 = 7.2G

Minimum Required DSI Clock Frequency = stream bit rate/ (2*number of DSI lanes) = 7.2G / (2*8) = 450MHz

These calculations assume you are using all 8 data lanes on the DSI side. The minimum required DSI clock frequency is 450MHz, which is supported on the DSI86 input side. The maximum frequency the MIPI input of the DSI can handle is 750MHz. So, the DSI86 can support this display.

Best, Allison

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SN65DSI86: Whether the resolution exceeds 6G can also be supported