• Locked Locked
  • Replies 9 replies
  • Subscribers 35 subscribers
  • Views 701 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB947-Q1: How to generate patterns used 947 internal clock and internal timing

user6105554
Prodigy 151 points
Part Number: DS90UB947-Q1


We want to set the patterns for the internal clock and internal timing of 947，But it didn't work

Our configuration is as follows.

AHW=1920
AVW=1080
HBP=20
VBP=8
HFP=20
VFP=24
HSW=20
VSW=2

PCLK=135

0x64 0x10 //disabled patttern
0x66 0x04
0x67 0xbc
0x66 0x05
0x67 0xa7
0x66 0x06
0x67 0x45
0x66 0x07
0x67 0x80
0x66 0x08
0x67 0x87
0x66 0x09
0x67 0x43
0x66 0x0a
0x67 0x14
0x66 0x0b
0x67 0x02
0x66 0x0c
0x67 0x14
0x66 0x0d
0x67 0x08
0x66 0x1a
0x67 0x09 //M=9
0x66 0x03
0x67 0x35 //N=53
0x65 0x04 //internal clk and timing
0x64 0x41

After 947 configuration，947,948 unlock，948 has no clock output

when set 947 reg 0xx65=0x04, is this set internal clock and internal PATGEN timing? are the M and N  settings correct？

  • TI__Guru** 109370 points

    Hello,

    due to the delay caused by the E2E maintenance, we will get back to you on Monday!

  • in reply to Hamzeh Jaradat
    TI__Mastermind 35105 points

    Hi,

    user6105554 said:
    when set 947 reg 0xx65=0x04, is this set internal clock and internal PATGEN timing? are the M and N  settings correct？

    The register setting is correct. I calculated an internal PCLK of (9/53 * 800 MHz) 135.85 MHz using the M and N settings.

    user6105554 said:
    After 947 configuration，947,948 unlock，948 has no clock output

    Are you forcing FPD-Link dual mode on the 947 (Register 0x5B)? When using the 800 MHz clock for PATGEN, it is recommended to force FPD-Link dual mode to prevent false operational detection.

    Regards,

    Jack

  • in reply to Jack Scherlag
    Prodigy 151 points

    we set 947 0x5b=0x23 in initialization,after the screen lights up normally then set pattern config,I think  the internal clock has not been generated。

  • in reply to user6105554
    TI__Mastermind 35105 points

    Hi,

    Are you still losing lock when configuring the PATGEN? If this is still happening, then we have more to suspect on the internal clock generation. Can you send the full script that is run on the 947?

    user6105554 said:
    after the screen lights up normally then set pattern config

    Are you currently able to send video from 947 to 948 without PATGEN? What does screen lights up normally mean?

    If you have an external video source going into the 947, try enabling the external video timing source for the PATGEN and see if it is successful.

    Regards,

    Jack

  • in reply to Jack Scherlag
    Prodigy 151 points

    hi，jack：

        this  is 947 948 init config,

    /*init 947*/
    0x03 0xda
    0x17 0x9e
    0x5b 0x23
    0x4f  0x80
    0x04 0x90
    /*init 948*/
    0x26 0x16
    0x27 0x16

    Are you currently able to send video from 947 to 948 without PATGEN? What does screen lights up normally mean?

       yes,without patgen,the screen is on.  screen lights up normally mean the screen is on and work 

    If you have an external video source going into the 947, try enabling the external video timing source for the PATGEN and see if it is successful.

       it is successful when select the external video timing source for the PATGEN

  • in reply to user6105554
    TI__Mastermind 35105 points

    Hi,

    user6105554 said:
     it is successful when select the external video timing source for the PATGEN

    I would continue using external video timing for PATGEN because it is more accurate to actual device operation. The internal timing and oscillator are irrelevant beyond PATGEN operation.

    Regards,

    Jack

  • in reply to Jack Scherlag
    Prodigy 151 points

    But sometimes it is necessary to use internal clock and timing to eliminate external influences and positioning the problem. PCLK 135M is not feasible, but 120M can be used when using internal clock timing

  • in reply to user6105554
    TI__Mastermind 35105 points

    Hi,

    I talked to the team about this issue and there are some additional configuration settings needed for the 947. The script I attached implements some of the errata items for the 947. Because the errata is NDA and this is a public forum, I can't discuss the errata in detail.

    Regards,

    Jack

    Fullscreen 947_Init.py Download 
    import time

# System dependant variables - adjust according to system
UB947 = 0x18        # 947 I2C Address
UB948 = 0x68        # Remote 948 Address


def pollstate():
    count = 0
    board.WriteI2C(UB947, 0x23, 0x80)
    board.WriteI2C(UB947, 0x24, 0x80)
    mask = int('11111', 2)
    state = board.ReadI2C(UB947, 0x24, 1)
    while (state & mask) != 27:  # 27 = 5'b11011
        time.sleep(0.01)  # 10ms delay
        state = board.ReadI2C(UB947, 0x24, 1)
        count = count + 1
        if count == 10:
            print
            "Error: Serializer is not in Normal state"
            return (1)

    board.WriteI2C(UB947, 0x23, 0x0)
    board.WriteI2C(UB947, 0x24, 0x0)

board.WriteI2C(UB948,0x4A,0x01) # Disable OLDI outputs on 948 to prevent screen glitches from appearing during the init process

##### Init A Sequence

board.WriteI2C(UB947,0x5B,0x03) # Force dual FPD-Link, disable reset on PLL frequency change

board.WriteI2C(UB947,0x16,0x02) # Adjust BCC watchdog timer to minimum

board.WriteI2C(UB947,0x04,0x90) # Prevent AVMUTE for non-HDCP systems

state_error = pollstate()  # Poll 947 state machine

if state_error == 1:
    print "Serializer not in normal state"

board.WriteI2C(UB947,0x40,0x10)
board.WriteI2C(UB947,0x41,0x49)
board.WriteI2C(UB947,0x42,0x16)
board.WriteI2C(UB947,0x41,0x47)
board.WriteI2C(UB947,0x42,0x20)
board.WriteI2C(UB947,0x42,0xA0)
board.WriteI2C(UB947,0x42,0x20)
board.WriteI2C(UB947,0x42,0x00)
board.WriteI2C(UB947,0x41,0x49)
board.WriteI2C(UB947,0x42,0x00)

time.sleep(0.01)

board.WriteI2C(UB948,0x01,0x01) # Digital reset to restart AEQ
time.sleep(0.1) # Allow time for 948 to relock
board.WriteI2C(UB948,0x4A,0x00) # Enable OLDI outputs on 948

#User defined programming sequence

board.WriteI2C(UB947, 0x03, 0xDA)
board.WriteI2C(UB947, 0x17, 0x9E)
board.WriteI2C(UB947, 0x4F, 0x80)
board.WriteI2C(UB948, 0x26, 0x16)
board.WriteI2C(UB948, 0x27, 0x16)

#PATGEN programming

board.WriteI2C(UB947,0x64, 0x10) //disabled patttern
board.WriteI2C(UB947,0x66, 0x04)
board.WriteI2C(UB947,0x67, 0xbc)
board.WriteI2C(UB947,0x66, 0x05)
board.WriteI2C(UB947,0x67, 0xa7)
board.WriteI2C(UB947,0x66, 0x06)
board.WriteI2C(UB947,0x67, 0x45)
board.WriteI2C(UB947,0x66, 0x07)
board.WriteI2C(UB947,0x67, 0x80)
board.WriteI2C(UB947,0x66, 0x08)
board.WriteI2C(UB947,0x67, 0x87)
board.WriteI2C(UB947,0x66, 0x09)
board.WriteI2C(UB947,0x67, 0x43)
board.WriteI2C(UB947,0x66, 0x0a)
board.WriteI2C(UB947,0x67, 0x14)
board.WriteI2C(UB947,0x66, 0x0b)
board.WriteI2C(UB947,0x67, 0x02)
board.WriteI2C(UB947,0x66, 0x0c)
board.WriteI2C(UB947,0x67, 0x14)
board.WriteI2C(UB947,0x66, 0x0d)
board.WriteI2C(UB947,0x67, 0x08)
board.WriteI2C(UB947,0x66, 0x1a)
board.WriteI2C(UB947,0x67, 0x09) //M=9
board.WriteI2C(UB947,0x66, 0x03)
board.WriteI2C(UB947,0x67, 0x35) //N=53
board.WriteI2C(UB947,0x65, 0x04) //internal clk and timing
board.WriteI2C(UB947,0x64, 0x41)

  • in reply to Jack Scherlag
    Prodigy 151 points

    this is solve my problem, thank you