DS90UB941AS-Q1: Margin analysis pass but its DSI clock jitter is slightly high.

Randy Lee

Part Number: DS90UB941AS-Q1

HI TI experts,

Are there any problems if the FPDlink passes the margin analysis program (MAP) test but fails the input clock jitter test when using DSI as REFCLK ?

How should I assess the functionality of the FPD link based on the MAP test results if they all pass?

Here are the conditions in my test :

Configuration :

1. Single FPD link

2. Pixel clock : 36MHz

3. DSI clock : 108MHz, 4 lanes

4. FPD link length : 3m

From the above configuration, the maximum allowable total jitter is approximately 238ps. However, the measured total jitter can reach up to 250ps.

over 2 years ago

0 Jack Scherlag over 2 years ago

TI__Mastermind 33715 points

Hi Randy,

With the DSI clock jitter marginally beyond the maximum specification, this could manifest as timing issues on the deserializer output and artefacts on the display screen. This might not be immediately obvious because the measured total jitter is not far outside the max allowable but time and aging could make it more likely to pop up.

Randy Lee said:
How should I assess the functionality of the FPD link based on the MAP test results if they all pass?

Based on the MAP results passing, the FPD-Link is functioning as expected. If the video output is not working properly due to DSI clock jitter, this is an error due to the DSI generator not meeting the serializer specifications.

Does the DSI generator you are using have specifications for clock jitter? Is this dependent on a reference clock the DSI generator is using?

Best,

Jack

0 Randy Lee over 2 years ago in reply to Jack Scherlag

Prodigy 50 points

Hi Jack,

Thanks for your feedback.

Since our DSI clock doesn't have a jitter specification, we're going to use an external clock as our reference instead.

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DS90UB941AS-Q1: Margin analysis pass but its DSI clock jitter is slightly high.