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DP83869HM: TX issue ?

Guillaume Seuru
Prodigy 10 points
Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Hello,

DP83869 is used in rgmii copper mode, connected to a SOC through rgmii/mdio, on a custom board.

Linux driver is used on the SOC. PHY initialization seems ok (detection on mdio, configuration).

Default configuration is used.

PHY LED configuration has been changed to have link-up / tx activity only / rx activity only.

- Cable connection between the custom board and a PC :
link-up LED becomes stable ON.
PC indicates link-up, auto-negotiated 10Mbps - full, the SOC too.

- Ping from PC:
rx LED blink
tx LED blink
tcpdump on the SOC displays the ARP received from the PC and the answers sent back to it.
PC does not receive the answers. ping fails.

- Ping from SOC:
rx LED off
tx LED blink
PC does not receive the ARP requests. ping fails.

CLK_O_SEL (IO_MUX_CFG register) has been modified to monitor TX clock on scope:
Channel A transmit clock: CLK_OUT = 25MHz
Channel B transmit clock: CLK_OUT = 25MHz
Channel C transmit clock: CLK_OUT = 25MHz
Channel D transmit clock: CLK_OUT = 25MHz
Default configuration (ref clock): CLK_OUT = 25MHz

Shoud we have 2.5MHz since the link is 10Mbps?

Can we say RX is ok ? SOC-PHY connection is ok ?

I don't know where is the issue, what I have to check and the tests I could do...

I can provide PHY register values if needed.

Thanks for your help.

  • 0
    TI__Mastermind 19621 points

    Hi Guillaume,

    Just to be sure that I understand your setup:

    SOC <-RGMII-> 869 <-Ethernet Cable-> PC

    The problem you're seeing is that the SOC can receive communication from the PC, but the PC does not receive anything from the SOC; correct?

    Below are a few suggestions that may help you debug your issue:

    • This could be because of RGMII Delays, here are some registers to play with. Suggest 867 Debug Guide.
    • 2 Register Write to change CLKOUT Speed
      • Reg 0xC6 = 0x10 (not included in datasheet)
      • 0x170[12:8] may be modified according to datasheet.

    Please let me know if this helps.

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    Thanks for your help.

    Indeed this was related to RGMII delays.

    Now we face to 10Mbits auto negotation whereas both phy are 1G capable. Could it be related to delay configuration values ?

    Regards

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    Is the mapping identical for 867 and 869?

    For instance link quality MSE registers are located @0x225/0x265/0x2a5/0x2e5 ?

    Read from phy 869:
    0x225: from 20 to100
    0x265: 0x7fff
    0x2a5: 0x7fff
    0x2e5: 0x7fff

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    Referring to your previous question, you are linking up in 10 Mbps, but you want 1000 correct?

    Could you read Register 0x01DF? This will confirm the mode the 869 is in.

    I will need to get back to you on the MSE registers, I can respond on Tuesday (we have a holiday on Monday).

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    869 is linking up in 10Mbps, expected is 1000.

    It takes a long time before linking up (1 minute or more).

    0x1fd - OP_MODE_DECODE register is set to 0x0 by the linux driver and our device tree.

    This register has been forced to 0x40 to follow datasheet rgmii to copper ethernet mode sequence. Same result.

    Regards,

    Guillaume

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    The MSE registers are located @0x225/0x265/0x2a5/0x2e5. 

    I believe the reason you're seeing the 0x7FFF values are because you're linked up at 10 Mbps.

    Could you try the following Register Writes:

    Address Write Value Remark
    0x0004 0001 De-advertises 10M & 100M Speeds
    0x0009 0300 Advertises 1000M Speed
    0x001F 4000 Soft-Reset PHY 

    These will help you link up at 1000 Mbps. 

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    We tried this by deactivating 10M&100M advertising but the 869 is unable to link up. As soon as the phy soft reset is done, link is down, it tries to connect but never links up.

    We don't have standard rj45 connector on our board, but specific connector and a custom cable (half-meter) with a rj45 at the end.

    We have several custom cables and 4 869-phys:

    With one of these, phy never links up

    With another one, 10M link-up after 30 seconds (always the same time)

    With another one, 10M link-up after 30 seconds or sometimes several minutes

    Board and cable schematics have been checked.

    Please note that we have 4 instances of 869 phy on our board and all of them behaves the same way, linking-up at 10M.

    ethtool running on the PC warns to check our cable.

    Can we learn something from MSE registers? (one or more ports are unusable ?)

    MSE registers are read every 5s:

    - Before link-up: most of the time MSE register port A < 100 and port B/C/D = 0x7fff. Sometimes the 4 ports are around 2000/3000 in the same time.

    - After link-up: all MSE registers = 0x7fff

    Thanks for your help.

    Regards,

    Guillaume

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    Could you provide a block diagram of your setup?

    Guillaume Seuru said:
    We don't have standard rj45 connector on our board, but specific connector and a custom cable (half-meter) with a rj45 at the end.

    This connector setup in specific is what I want more detail on. Do you have a transformer on the board?

    Could you also try: 

    • Check the Link-Partner's advertised speeds
      • Register 0x5
        • Tells us if LP advertises 10/100
      • Register 0xA
        • Tells us if LP advertises 1000
    • Could you try using another 869 as the Link Partner?

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    Here is the schematic. I don't know if it will readable. Please let me know.

    We tried with a short rj45 cable connected tothe transformer, but we have the same behaviour, linking-up 10M.

    We tried a loopback 869-869, linking-up 10M.

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    As you suspected, the schematic is difficult to read. Could you send it as a pdf?

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    I can't get your last message on the forum. So I reply here.

    The tests you requested:

    Advertising 10M/100M enabled (ANAR = 0x0de1):
    [  171.402247] PHY_STATUS = 00000002 <= cable unplugged
    [  172.426244] PHY_STATUS = 00000302
    [  173.450292] PHY_STATUS = 00000002
    [  174.474253] PHY_STATUS = 00000302
    [  175.498245] PHY_STATUS = 00000302
    [  176.522244] PHY_STATUS = 00000302
    [  177.546247] PHY_STATUS = 00000002
    [  178.570246] PHY_STATUS = 00000302
    [  179.594301] PHY_STATUS = 00000302
    [  180.618254] PHY_STATUS = 00000302
    [  181.642246] PHY_STATUS = 00000002
    [  182.666246] PHY_STATUS = 00000302 <= cable plugged
    [  183.690249] PHY_STATUS = 00001302
    [  184.714246] PHY_STATUS = 0000b302
    [  185.738303] PHY_STATUS = 00000302
    [  186.762254] PHY_STATUS = 00001002
    [  187.786246] PHY_STATUS = 0000b002
    [  188.810241] PHY_STATUS = 00000102
    [  189.834249] PHY_STATUS = 00001102
    [  190.858303] PHY_STATUS = 00001102
    [  191.882257] PHY_STATUS = 00000002
    [  192.906247] PHY_STATUS = 00000302
    [  193.930248] PHY_STATUS = 00001002
    [  194.954250] PHY_STATUS = 00001302
    [  195.978248] PHY_STATUS = 00000302
    [  197.002304] PHY_STATUS = 00001302
    [  198.026261] PHY_STATUS = 00001302
    [  199.050250] PHY_STATUS = 00000002
    [  200.074244] PHY_STATUS = 00000302
    [  201.098243] PHY_STATUS = 00001302
    [  202.122244] PHY_STATUS = 00001002
    [  203.146297] PHY_STATUS = 00000302
    [  204.170254] PHY_STATUS = 00001002
    [  205.194313] PHY_STATUS = 00003c02
    [  205.194385] pfeng 46000000.pfe pfe0: Set TX clock to 2500000Hz
    [  205.194422] pfeng 46000000.pfe pfe0: Link is Up - 10Mbps/Full - flow control rx/tx
    [  206.218056] PHY_STATUS = 00002c02 <= link-up
    [  207.242056] PHY_STATUS = 00002c02
    [  208.266054] PHY_STATUS = 00002c02
    [  209.290091] PHY_STATUS = 00002c02
    [  210.314055] PHY_STATUS = 00002c02
    [  211.338057] PHY_STATUS = 00002c02
    [  212.362051] PHY_STATUS = 00002c02
    [  213.386054] PHY_STATUS = 00002c02

    Advertising 10M/100M disabled (ANAR=0x0001 + GEN_CFG2 bits 6&9 = 0):
    [   50.698594] PHY_STATUS           =00000002  <= cable unplugged
    [   51.722594] PHY_STATUS           =00000002
    [   52.746594] PHY_STATUS           =00000302
    [   53.770643] PHY_STATUS           =00000302
    [   54.794622] PHY_STATUS           =00000302
    [   55.818611] PHY_STATUS           =00000302
    [   56.842604] PHY_STATUS           =00000002
    [   57.866607] PHY_STATUS           =00000002
    [   58.890642] PHY_STATUS           =00000002
    [   59.914622] PHY_STATUS           =00000302
    [   60.938618] PHY_STATUS           =00000302  <= cable plugged
    [   61.962615] PHY_STATUS           =00001002
    [   62.986617] PHY_STATUS           =00001002
    [   64.010610] PHY_STATUS           =00000002
    [   65.034640] PHY_STATUS           =00000002
    [   66.058595] PHY_STATUS           =00001302
    [   67.082593] PHY_STATUS           =00001002
    [   68.106595] PHY_STATUS           =00000002
    [   69.130594] PHY_STATUS           =00001302
    [   70.154593] PHY_STATUS           =00001302
    [   71.178650] PHY_STATUS           =00000002
    [   72.202614] PHY_STATUS           =00000002
    [   73.226605] PHY_STATUS           =00001002
    [   74.250604] PHY_STATUS           =00001302
    [   75.274610] PHY_STATUS           =00000002
    [   76.298608] PHY_STATUS           =00001302
    [   77.322646] PHY_STATUS           =00001302
    [   78.346612] PHY_STATUS           =00000002
    [   79.370608] PHY_STATUS           =00001002

    I added code in the TI DP83869 linux driver to read phy registers in the read status function, called every 1s.
    Not shown in the log, but sometimes PHY_STATUS is read to 0xbXXX, whatever 10M/100M advertising is enabled or not.

    Contrary to what I wrote in my previous message, no link-up between 869 and PC when ANAR=0x0001 (10M/100M advertising disable), not able to link-up @10M.

    When 10M/100M advertising is enabled, there is a slight blink of the phy activity LED every 5s, until it gets fixed once linked-up @10M.
    This slight blink does not happen when 10M/100M advertising is disabled.

    Regards,
    Guillaume

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    Thank you for performing this experiment. I tried this in our lab as well and am seeing PHY_STATUS = AC02 when cable is connected and link is up. When cable is disconnected, PHY_STATUS reads 0302 or 0002.

    Please allow me another day to consult with my team for further debug steps.

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    2 more tests:

    - Test 1:
    Our board has a GPIO connected to RESET_N 869 pin. Board is powered on, Linux is started, 869 initialized, .... The eth interface is set to down (ifconfig down) and we let it down. The RESET_N pin is set to low then to high. The interface is never started again, so no software configures the 869. Its configuration is provided by the straps. In that case, link-up @10M (according to ethtool runnning on the PC connected to the board).

    - Test 2:
    The MDIO accesses have been spyed during 869 initialization. I hope there is something wrong here...

    [ 2424.172429] pfeng 46000000.pfe: W: phyreg=001f, phydata=8000  => W GEN_CTRL = 0x8000 (phy reset)
    [ 2424.172655] pfeng 46000000.pfe: R: phyreg=0014, phyval=29c7   => R GEN_CFG2 = 0x29c7
    [ 2424.172667] pfeng 46000000.pfe: W: phyreg=0014, phydata=2bc7  => W GEN_CFG2 = 0x2bc7 (enable speed optimization)
    [ 2424.172797] pfeng 46000000.pfe: R: phyreg=0014, phyval=2bc7   => R GEN_CFG2 = 0x2bc7
    [ 2424.172818] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f  
    [ 2424.172880] pfeng 46000000.pfe: W: phyreg=000e, phydata=01df
    [ 2424.172943] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.173007] pfeng 46000000.pfe: W: phyreg=000e, phydata=0040  => W OP_MODE_DECODE = 0x0040 (datasheet §9.4.8.1)
    [ 2424.173078] pfeng 46000000.pfe: W: phyreg=0000, phydata=1140  => W BMCR = 0x1140  (datasheet §9.4.8.1)
    [ 2424.173150] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.173213] pfeng 46000000.pfe: W: phyreg=000e, phydata=0004
    [ 2424.173364] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.173428] pfeng 46000000.pfe: W: phyreg=000e, phydata=01e1  => W ANAR = 0x01e1  (datasheet §9.4.8.1)
    [ 2424.173497] pfeng 46000000.pfe: W: phyreg=0009, phydata=0300  => W GEN_CFG1 = 0x0300  (datasheet §9.4.8.1)
    [ 2424.173627] pfeng 46000000.pfe: R: phyreg=0010, phyval=5048   => R PHY_CONTROL = 0x5048
    [ 2424.173642] pfeng 46000000.pfe: W: phyreg=0010, phydata=5048  => W PHY_CONTROL = 0x5048  (datasheet §9.4.8.1)
    [ 2424.173710] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.173772] pfeng 46000000.pfe: W: phyreg=000e, phydata=0009
    [ 2424.173835] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.173897] pfeng 46000000.pfe: W: phyreg=000e, phydata=0300  => W GEN_CFG1 = 0x0300
    [ 2424.173965] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.174714] pfeng 46000000.pfe: W: phyreg=000e, phydata=001f
    [ 2424.175036] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.175130] pfeng 46000000.pfe: W: phyreg=000e, phydata=4000  => W GEN_CTRL = 0x4000  (datasheet §9.4.8.1)
    [ 2424.175397] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.175718] pfeng 46000000.pfe: W: phyreg=000e, phydata=0031
    [ 2424.175812] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.176149] pfeng 46000000.pfe: R: phyreg=000e, phyval=10b0   => R GEN_CFG3 = 0x10b0
    [ 2424.176162] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.176348] pfeng 46000000.pfe: W: phyreg=000e, phydata=0170
    [ 2424.176430] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.176687] pfeng 46000000.pfe: R: phyreg=000e, phyval=0c0e   => R IO_MUX_CFG = 0x0c0e
    [ 2424.176699] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.176762] pfeng 46000000.pfe: W: phyreg=000e, phydata=0170
    [ 2424.176824] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.176886] pfeng 46000000.pfe: W: phyreg=000e, phydata=0b0e  => W IO_MUX_CFG = 0x0b0e
    [ 2424.176950] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.177012] pfeng 46000000.pfe: W: phyreg=000e, phydata=0170
    [ 2424.177075] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.177202] pfeng 46000000.pfe: R: phyreg=000e, phyval=0b0e   => R IO_MUX_CFG = 0x0b0e
    [ 2424.177220] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.177310] pfeng 46000000.pfe: W: phyreg=000e, phydata=0086
    [ 2424.177373] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.177436] pfeng 46000000.pfe: W: phyreg=000e, phydata=7fd0  => W ANA_RGMII_DLL_CTRL = 0x7fd0
    [ 2424.177498] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.177560] pfeng 46000000.pfe: W: phyreg=000e, phydata=0086
    [ 2424.177622] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.177747] pfeng 46000000.pfe: R: phyreg=000e, phyval=03d0   => R ANA_RGMII_DLL_CTRL = 0x03d0
    [ 2424.177763] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.177825] pfeng 46000000.pfe: W: phyreg=000e, phydata=0032
    [ 2424.177887] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.178012] pfeng 46000000.pfe: R: phyreg=000e, phyval=00d0   => R RGMII_CTRL = 0x00d0
    [ 2424.178029] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.178091] pfeng 46000000.pfe: W: phyreg=000e, phydata=0032
    [ 2424.178153] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.178216] pfeng 46000000.pfe: W: phyreg=000e, phydata=00d1  => W RGMII_CTRL = 0x00d1
    [ 2424.178349] pfeng 46000000.pfe: R: phyreg=0014, phyval=2bc7   => R GEN_CFG2 = 0x2bc7
    [ 2424.178422] pfeng 46000000.pfe: R: phyreg=0014, phyval=2bc7   => R GEN_CFG2 = 0x2bc7
    [ 2424.178438] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f  
    [ 2424.178500] pfeng 46000000.pfe: W: phyreg=000e, phydata=01df
    [ 2424.178562] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.178624] pfeng 46000000.pfe: W: phyreg=000e, phydata=0040  => W OP_MODE_DECODE = 0x0040
    [ 2424.178692] pfeng 46000000.pfe: W: phyreg=0000, phydata=1140  => W BMCR = 0x1140
    [ 2424.178760] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.178824] pfeng 46000000.pfe: W: phyreg=000e, phydata=0004
    [ 2424.178886] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.178948] pfeng 46000000.pfe: W: phyreg=000e, phydata=01e1  => W ANAR = 0x01e1
    [ 2424.179015] pfeng 46000000.pfe: W: phyreg=0009, phydata=0300  => W GEN_CFG1 = 0x0300
    [ 2424.179148] pfeng 46000000.pfe: R: phyreg=0010, phyval=5048   => R PHY_CONTROL = 0x5048
    [ 2424.179163] pfeng 46000000.pfe: W: phyreg=0010, phydata=5048  => W PHY_CONTROL = 0x5048
    [ 2424.179231] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.179293] pfeng 46000000.pfe: W: phyreg=000e, phydata=0009
    [ 2424.179356] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.179420] pfeng 46000000.pfe: W: phyreg=000e, phydata=0300  => W GEN_CFG1 = 0x0300
    [ 2424.179488] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.179550] pfeng 46000000.pfe: W: phyreg=000e, phydata=001f
    [ 2424.179613] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.179676] pfeng 46000000.pfe: W: phyreg=000e, phydata=4000  => W GEN_CTRL = 0x4000
    [ 2424.179745] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.179807] pfeng 46000000.pfe: W: phyreg=000e, phydata=0031
    [ 2424.179869] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.179995] pfeng 46000000.pfe: R: phyreg=000e, phyval=10b0   => R GEN_CFG3 = 0x10b0
    [ 2424.180005] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.180068] pfeng 46000000.pfe: W: phyreg=000e, phydata=0170
    [ 2424.180131] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.180257] pfeng 46000000.pfe: R: phyreg=000e, phyval=0b0e   => R IO_MUX_CFG = 0x0b0e
    [ 2424.180267] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.180330] pfeng 46000000.pfe: W: phyreg=000e, phydata=0170
    [ 2424.180393] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.180519] pfeng 46000000.pfe: R: phyreg=000e, phyval=0b0e   => R IO_MUX_CFG = 0x0b0e
    [ 2424.180535] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.180598] pfeng 46000000.pfe: W: phyreg=000e, phydata=0086
    [ 2424.180660] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.180722] pfeng 46000000.pfe: W: phyreg=000e, phydata=7fd0  => W ANA_RGMII_DLL_CTRL = 0x7fd0
    [ 2424.180785] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.180849] pfeng 46000000.pfe: W: phyreg=000e, phydata=0086
    [ 2424.180911] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.181037] pfeng 46000000.pfe: R: phyreg=000e, phyval=03d0   => R ANA_RGMII_DLL_CTRL = 0x7fd0
    [ 2424.181052] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.181115] pfeng 46000000.pfe: W: phyreg=000e, phydata=0032
    [ 2424.181177] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.181302] pfeng 46000000.pfe: R: phyreg=000e, phyval=00d1   => R RGMII_CTRL = 0x00d1
    [ 2424.181318] pfeng 46000000.pfe: W: phyreg=000d, phydata=001f
    [ 2424.181381] pfeng 46000000.pfe: W: phyreg=000e, phydata=0032
    [ 2424.181444] pfeng 46000000.pfe: W: phyreg=000d, phydata=401f
    [ 2424.181507] pfeng 46000000.pfe: W: phyreg=000e, phydata=00d1  => W RGMII_CTRL = 0x00d1
    [ 2424.181575] pfeng 46000000.pfe: W: phyreg=0012, phydata=0000  => W INTERRUPT_MSK = 0x0000
    [ 2424.181639] pfeng 46000000.pfe: W: phyreg=0012, phydata=0000  => W INTERRUPT_MSK = 0x0000
    [ 2424.181765] pfeng 46000000.pfe: R: phyreg=0013, phyval=0000   => R INTERRUPT_STS = 0x0000
    [ 2424.181838] pfeng 46000000.pfe: R: phyreg=0000, phyval=1140   => R BMCR = 0x1140
    [ 2424.181865] pfeng 46000000.pfe pfe0: PHY [PFEng Ethernet MDIO.0:00] driver [TI DP83869] (irq=POLL)
    [ 2424.181898] pfeng 46000000.pfe pfe0: configuring for phy/rgmii-txid link mode
    [ 2424.182045] pfeng 46000000.pfe: R: phyreg=0000, phyval=1140   => R BMCR = 0x1140
    [ 2424.182303] pfeng 46000000.pfe: R: phyreg=0004, phyval=01e1   => R ANAR = 0x01e1
    [ 2424.182314] pfeng 46000000.pfe: W: phyreg=0004, phydata=0de1  => W ANAR = 0x0de1
    [ 2424.182441] pfeng 46000000.pfe: R: phyreg=0001, phyval=7949   => R BMSR = 0x7949
    [ 2424.182513] pfeng 46000000.pfe: R: phyreg=0009, phyval=0300   => R GEN_CFG1 = 0x0300
    [ 2424.182586] pfeng 46000000.pfe: R: phyreg=0000, phyval=1140   => R BMCR = 0x1140
    [ 2424.182595] pfeng 46000000.pfe: W: phyreg=0000, phydata=1340  => W BMCR = 0x1340 (restart auto-negotiation)
    [ 2424.182724] pfeng 46000000.pfe: R: phyreg=0000, phyval=1140   => R BMCR = 0x1140
    [ 2424.182796] pfeng 46000000.pfe: R: phyreg=0001, phyval=7949   => R BMSR = 0x7949
    [ 2424.182869] pfeng 46000000.pfe: R: phyreg=0001, phyval=7949   => R BMSR = 0x7949
    [ 2424.182941] pfeng 46000000.pfe: R: phyreg=0009, phyval=0300   => R GEN_CFG1 = 0x0300
    [ 2424.183016] pfeng 46000000.pfe: R: phyreg=000a, phyval=0000   => R GEN_STATUS1 = 0x0000
    [ 2425.193386] pfeng 46000000.pfe: R: phyreg=0000, phyval=1140   => R BMCR = 0x1140
    [ 2425.193470] pfeng 46000000.pfe: R: phyreg=0001, phyval=7949   => R BMSR = 0x7949

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillame

    A few more suggestions:

    • Could you try a different cable?
    • SNLA239 Page 13 1000 Base Test Mode 2: 
      • With a Differential Probe could you probe several different places to confirm that a waveform is seen across all 4 channels.
        • Before RJ-45
          • Close to PHY
          • Before and After magnetics
        • At receiving end after your custom cable
      • Example Output

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    Measurements have been done in test mode 2:

    - At the end of cable:

    - Magnetics, phy side:

    - Magnetics, media side: no picture, but all look good.

    We tried with 2 sets of custom cables. At the end of cable we have:
    - Set 1: 1 port with 0.6V amplitude, 1 port with 0.4 (see picture), 2 lasts ports: 0,7V.
    - Set 2: all ports: 0,7V

    The 2 sets behave the same way (very long to link-up, always @10M).

    On the magnetics, media side: like your example output.

    On the magnetics, phy side: see picture.

    Regards,

    Guillaume

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    Thank you for the scope shots, you probed these on all 4 channels correct? 

    Let me recap a few test cases that we've tried so far:

    • Default Strap Config
      • Links up in 10 Mbps
    • Setting Register 0x04 & 0x09 to de-advertise 10/100 speeds
      • No Link
    • What happened when we disable bits 6 & 9 in Reg 0x14 (disable Speed optimization)?
      • Did it link up or show no link?

    In a previous reply an ETH tool warning was mentioned, saying check your cable; could you provide a snapshot of the full message?

    Could you link up two 869s together again (you mentioned before that it linked up at 10 Mpbs) and provide a register dump, 0x0-0x1F, for both 869 PHYs once they are linked up together? In this same configuration can you also run ethtool to check the status of the PHY? Does it say link is up, speed 10 mbps, etc aswell? Basically I want to check if Ethtool matches the information we are getting from the registers.

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,


    Measurements in test mode 2 have been done on the 4 ports. On 3 869s of our board.
    Same signals for each port (amplitude on port A phy 1 = port A phy 2 = port A phy 3...).


    Tests with the PC:

    Default strap config: I confirm, no link-up.

    - Test 1:
    De-advertise 10/100 (ANAR=0x0001, GEN_CFG1=0x0300)
    Speed optimization enable: GEN_FG2=0x2bc7
    => no link-up

    - Test 2:
    De-advertise 10/100 (ANAR=0x0001, GEN_CFG1=0x0300)
    Speed optimization disable: GEN_FG2=0x2987
    => no link-up

    - Test 3:
    Advertise 10/100 (ANAR=0x0de1, GEN_CFG1=0x0300)
    Speed optimization disable: GEN_FG2=0x2987
    => link-up 10M


    Test with 2 869s:

    Both 869s connect only if speed optimization enabled (GEN_CFG2=0x2bc7), whereas one 869 is able to connect to the PC usb-eth converter whatever the speed optimization option, enable or not.

    Register dump for phy 1 (once linked-up):
    BMCR         = 1140
    BMSR         = 796d
    PHYIDR1      = 2000
    PHYIDR2      = a0f3
    ANAR         = 0de1
    ALNPAR       = cc61
    ANER         = 006d
    ANNPTR       = 2001
    ANLNPTR      = 4800
    GEN_CFG1     = 0300
    GEN_STATUS1  = 0c00
    REGCR        = 401f
    ADDAR        = 0000
    1KSCR        = f000
    PHY_CONTROL  = 5048
    PHY_STATUS   = 2c02
    INT_MASK     = 0000
    INT_STATUS   = 0000
    GEN_CFG2     = 2bc7
    RX_ERR_CNT   = 0000
    BIST_CONTROL = 0000
    GEN_STATUS2  = 0040
    LEDS_CFG1    = 6150
    LEDS_CFG2    = 4444
    LEDS_CFG3    = 0002
    GEN_CFG4     = 0012
    GEN_CTRL     = 0000

    phy 2:
    BMCR         = 1140
    BMSR         = 796d
    PHYIDR1      = 2000
    PHYIDR2      = a0f3
    ANAR         = 0de1
    ALNPAR       = cc61
    ANER         = 006d
    ANNPTR       = 2001
    ANLNPTR      = 4800
    GEN_CFG1     = 0300
    GEN_STATUS1  = 0c00
    REGCR        = 401f
    ADDAR        = 0000
    1KSCR        = f000
    PHY_CONTROL  = 5048
    PHY_STATUS   = 2c02
    INT_MASK     = 0000
    INT_STATUS   = 0000
    GEN_CFG2     = 2bc7
    RX_ERR_CNT   = 0000
    BIST_CONTROL = 0000
    GEN_STATUS2  = 0040
    LEDS_CFG1    = 6150
    LEDS_CFG2    = 4444
    LEDS_CFG3    = 0002
    GEN_CFG4     = 0012
    GEN_CTRL     = 0000


    ethtool on both interfaces:

    Settings for pfe0:
            Supported ports: [ TP MII ]
            Supported link modes:   10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Half 1000baseT/Full
                                    1000baseX/Full
            Supported pause frame use: Symmetric Receive-only
            Supports auto-negotiation: Yes
            Supported FEC modes: Not reported
            Advertised link modes:  10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Half 1000baseT/Full
                                    1000baseX/Full
            Advertised pause frame use: Symmetric Receive-only
            Advertised auto-negotiation: Yes
            Advertised FEC modes: Not reported
            Link partner advertised link modes:  10baseT/Half 10baseT/Full
                                                 1000baseT/Half 1000baseT/Full
            Link partner advertised pause frame use: Symmetric Receive-only
            Link partner advertised auto-negotiation: Yes
            Link partner advertised FEC modes: Not reported
            Speed: 1000Mb/s
            Duplex: Full
            Port: Twisted Pair
            PHYAD: 0
            Transceiver: external
            Auto-negotiation: on
            MDI-X: Unknown
            Link detected: yes


    Settings for pfe1:
            Supported ports: [ TP MII ]
            Supported link modes:   10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Half 1000baseT/Full
                                    1000baseX/Full
            Supported pause frame use: Symmetric Receive-only
            Supports auto-negotiation: Yes
            Supported FEC modes: Not reported
            Advertised link modes:  10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Half 1000baseT/Full
                                    1000baseX/Full
            Advertised pause frame use: Symmetric Receive-only
            Advertised auto-negotiation: Yes
            Advertised FEC modes: Not reported
            Link partner advertised link modes:  10baseT/Half 10baseT/Full
                                                 1000baseT/Half 1000baseT/Full
            Link partner advertised pause frame use: Symmetric Receive-only
            Link partner advertised auto-negotiation: Yes
            Link partner advertised FEC modes: Not reported
            Speed: 1000Mb/s
            Duplex: Full
            Port: Twisted Pair
            PHYAD: 0
            Transceiver: external
            Auto-negotiation: on
            MDI-X: Unknown
            Link detected: yes

    ethtool shows it is linked-up @1000 but the PHY 1G led is off and PHY_STATUS register indicates linked @10M.
    In this case, not able to communicate between the 2 869s (the SOC is providing a 125MHz clock whereas 869s are connected @10M ?).

    Sometimes one of the 2 869s is indicated @1000M, and the other one @10M:
    Settings for pfe1:
            Supported ports: [ TP MII ]
            Supported link modes:   10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Half 1000baseT/Full
                                    1000baseX/Full
            Supported pause frame use: Symmetric Receive-only
            Supports auto-negotiation: Yes
            Supported FEC modes: Not reported
            Advertised link modes:  10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Half 1000baseT/Full
                                    1000baseX/Full
            Advertised pause frame use: Symmetric Receive-only
            Advertised auto-negotiation: Yes
            Advertised FEC modes: Not reported
            Link partner advertised link modes:  10baseT/Half 10baseT/Full
            Link partner advertised pause frame use: Symmetric Receive-only
            Link partner advertised auto-negotiation: Yes
            Link partner advertised FEC modes: Not reported
            Speed: 10Mb/s
            Duplex: Full
            Port: Twisted Pair
            PHYAD: 0
            Transceiver: external
            Auto-negotiation: on
            MDI-X: Unknown
            Link detected: yes


    The 1st tests with the PC were done with a usb-eth converter.
    When using the PC internal NIC and when the link is up, ethtool on the SOC shows 1000M and ethtool on the PC shows 10M.

    It seems (by adding traces in the linux drivers), that GEN_STATUS1 bit 11 is read by linux to know the negotiated speed and to provide the right clock to the phy, whatever the PHY_STATUS register value:
    When linux reads ALNPAR=0xcc61 and GEN_STATUS1 = 0x0000, it says 10M.
    When linux reads ALNPAR=0xc1e1 and GEN_STATUS1 = 0x0800, it says 1000M.

    Regards

    Guillaume

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    Thank you for providing the tests above, they were helpful for the debug.

    When you connect to the PC in 10 Mbps, are you able to ping in both directions? Also I am unsure why Ethtool says 1000 and the PHY registers say 10.

    Regarding the Test with 2 869s:

    Guillaume Seuru said:
    ANAR         = 0de1
    ALNPAR       = cc61
    • ANAR (advertise their capabilities) 
      • Both advertising 10/100
    • ALNPAR (link partner's advertised capabilities) 
      • Both PHYs see only 10 advertised, neither see 100
        • Not sure why this would be the case
    Guillaume Seuru said:
    GEN_CFG1     = 0300
    GEN_STATUS1  = 0c00
    • GEN_CFG1 (advertised capabilities)
      • Both advertise 1000Base-T
    • GEN_STATUS1
      • Both see Link partner advertises 1000Base-T
      • But Master/Slave has not been resolved.

    The screenshot below is of some register reads I did when I connected two 869 EVM boards at 1000BASE-T.

    Register 1 shows that link is down, then up (read before and after connecting ethernet cable).

    Register 4 & 5 show that both PHYs are advertising and receiving the 10/100 advertisements from their link partner.

    Register 9 & A show that both PHY's are advertising and receiving the 1000Base-T advertisement from their link partner.

    And it shows that one has configured itself to a master and the other to a slave. At this moment I don't know why they wouldn't resolve this during auto-negotiation, but could you try again and manually configure one to Master and the other to Slave? This can be done by enabling Bit [12:11] in Register 0x9 GEN_CFG1.

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    When connected to the PC @10M, I am able to ping in both directions.

    Test 1 : 869s loopback, force one to slave mode, one to master mode:

    PID=111 phydev=PFEng Ethernet MDIO.1
    BMCR                 = 1140
    BMSR                 = 796d
    PHYIDR1              = 2000
    PHYIDR2              = a0f3
    ANAR                 = 0de1
    ALNPAR               = cc61
    ANER                 = 006d
    ANNPTR               = 2001
    ANLNPTR              = 4800
    GEN_CFG1             = 1b00
    GEN_STATUS1          = 0c00
    REGCR                = 401f
    ADDAR                = 0000
    1KSCR                = f000
    PHY_CONTROL          = 5048
    PHY_STATUS           = 2c02
    INT_MASK             = 0000
    INT_STATUS           = 0000
    GEN_CFG2             = 2bc7
    RX_ERR_CNT           = 0000
    BIST_CONTROL         = 0000
    GEN_STATUS2          = 0040
    LEDS_CFG1            = 6150
    LEDS_CFG2            = 4444
    LEDS_CFG3            = 0002
    GEN_CFG4             = 0012
    GEN_CTRL             = 0000
    PID=97 phydev=PFEng Ethernet MDIO.0
    BMCR                 = 1140
    BMSR                 = 796d
    PHYIDR1              = 2000
    PHYIDR2              = a0f3
    ANAR                 = 0de1
    ALNPAR               = cc61
    ANER                 = 006d
    ANNPTR               = 2001
    ANLNPTR              = 4800
    GEN_CFG1             = 1300
    GEN_STATUS1          = 0c00
    REGCR                = 401f
    ADDAR                = 0000
    1KSCR                = f000
    PHY_CONTROL          = 5048
    PHY_STATUS           = 2c02
    INT_MASK             = 0000
    INT_STATUS           = 0000
    GEN_CFG2             = 2bc7
    RX_ERR_CNT           = 0000
    BIST_CONTROL         = 0000
    GEN_STATUS2          = 0040
    LEDS_CFG1            = 6150
    LEDS_CFG2            = 4444
    LEDS_CFG3            = 0002
    GEN_CFG4             = 0012
    GEN_CTRL             = 0000

    => GEN_STATUS1 show both in slave mode

    Test 2 : 869s loopback, one phy slave mode, one phy master mode, autoneg disabled, fixed 1000M:
    => no link-up

    PID=97 phydev=PFEng Ethernet MDIO.1
    BMCR                 = 0140
    BMSR                 = 7949
    PHYIDR1              = 2000
    PHYIDR2              = a0f3
    ANAR                 = 0de1
    ALNPAR               = 0000
    ANER                 = 0064
    ANNPTR               = 2001
    ANLNPTR              = 0000
    GEN_CFG1             = 1b00
    GEN_STATUS1          = 0000
    REGCR                = 401f
    ADDAR                = 0000
    1KSCR                = f000
    PHY_CONTROL          = 5048
    PHY_STATUS           = a802
    INT_MASK             = 0000
    INT_STATUS           = 0040
    GEN_CFG2             = 2bc7
    RX_ERR_CNT           = 0000
    BIST_CONTROL         = 0000
    GEN_STATUS2          = 0040
    LEDS_CFG1            = 6150
    LEDS_CFG2            = 4444
    LEDS_CFG3            = 0002
    GEN_CFG4             = 0012
    GEN_CTRL             = 0000
    PID=59 phydev=PFEng Ethernet MDIO.0
    BMCR                 = 0140
    BMSR                 = 7949
    PHYIDR1              = 2000
    PHYIDR2              = a0f3
    ANAR                 = 0de1
    ALNPAR               = 0000
    ANER                 = 0064
    ANNPTR               = 2001
    ANLNPTR              = 0000
    GEN_CFG1             = 1300
    GEN_STATUS1          = 0000
    REGCR                = 401f
    ADDAR                = 0000
    1KSCR                = f000
    PHY_CONTROL          = 5048
    PHY_STATUS           = a802
    INT_MASK             = 0000
    INT_STATUS           = 0040
    GEN_CFG2             = 2bc7
    RX_ERR_CNT           = 0000
    BIST_CONTROL         = 0000
    GEN_STATUS2          = 0040
    LEDS_CFG1            = 6150
    LEDS_CFG2            = 4444
    LEDS_CFG3            = 0002
    GEN_CFG4             = 0012
    GEN_CTRL             = 0000   

     =>end

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    We do not support Forced 1000 Mbps (essentially what you tried doing in Test 2). Force 100 Mbps is supported, could you try again with 100 Mbps? 

    A 0x1f =4000 at the end of your script wouldn't hurt.

    Have you tried running any of the Compliance tests? This would be another good way to validate your signal. 

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    TI__Mastermind 19621 points

    Hi Guillaume,

    Another customer was seeing a very similar link up issue, their problem was resolved when they notice the RBIAS resistor they had was 1.1kOhm instead of 11kOhm. Could you double check this resistor and confirm if you see 1V across this resistor?

    Regards,

    Alvaro

  • 0 in reply to Alvaro (Al-vuh-roe) Reyes
    Prodigy 10 points

    Hi Alvaro,

    Unfortunately we have 1V across the RBIAS resistor.

    What is exactly the link-up issue the another customer had ?

    Has the dp83869 already been tested with mirror mode disabled ?

    Regards,

    Guillaume

  • 0 in reply to Guillaume Seuru
    TI__Mastermind 19621 points

    Hi Guillaume,

    The customer had the issue where it was linking up in 10 Mbps instead of 1000, similar to yours. Mirror Mode disabled has been tested and is known to work. 

    Open Items:

    • Can you confirm that the RBIAS Resistor value is 11 kΩ?
    • Can you redo Test 2, except for 100 Mbps instead of 1000
      • Forced Gigabit is not supported, the results from this are inconclusive.
      • In Test 1 it concerns me that both PHYs advertise 100 mbps modes (seen in ANAR Register = 0DE1)
        • But ALNPAR Register (abilities of link-partner) = CC61 which isn't showing 100 Mbps advertised modes 
        • GEN_STATUS_1 (shows LP Gigabit abilities) = 1B00, which shows gigabit advertised.

    Regards,

    Alvaro