DP83867E: SGMII Half/Full Duplex?

Hi Matthew,

The SGMII protocol is always full duplex. For 10Mbps operation, the data rate stays at 625Mhz, but each byte is elongated by 100x. The SGMII speed shall auto-negotiate to that of the copper side. 

Are you seeing issues with auto-negotiation or throughput?

Thanks,

David

Based on registers read from the PHY, it appears our auto negotiation is failing.  I feel register 0x1 and 0x37 are conflicting.  Auto-negotiation complete, but x37 says it's still running.

Reg 0x0: 0x10c0

Reg 0x1: 0x796d

Reg 0x10: 0x5848

Reg 0x14: 0x29c7

Reg 0x37: 0x0040

Hi Matthew,

Register one indicates that the copper side auto-negotiation has completed. Register 0x37 indicates that the SGMII auto-negotiation is not completed. These are separate items. Can you share a complete register dump from 0x0-0x1F, 0x31, 0x6E, 0x6F?

Have you tried transferring data? Is it unsuccessful?

Can you also share the schematic?

Thanks,

David

I've tried pinging across the link without success.  I'll work on getting the register dump.  I do not have a schematic to share, unfortunately.  

Thank you. Let me know when you have the register dump.

Thanks,

David

Missed grabbing the last 3 you requested.  I'll work on those.

Hello,

I work on the same team as David. He is currently OoO and will be back next week.

Sincerely,

Gerome

Hi Matthew,

Apologies for the delay. Can you share images of your setup or a block diagram? I would like to understand how the interfaces are connected and what link partner is being used. 

Also if you could share the register reads of 0x31, 0x6E, 0x6F.

Thanks,

David

I'm trying to get these registers for you.  I'm sorry for the delay.  Hardware access limitations.

Hi Matthew,

Okay, please let me know when you have the register reads and setup pictures/block diagrams.

Thanks,

David

Hi Matthew, 

Great to hear the issue was found! If you don't mind, could you share more details of the firmware fix, as it will be helpful for future viewers of this thread.

Thanks,

David

My understanding - It was a coordination of PHY and logic resets that was not being handled, adequately.  Firmware resets and hardware resets were not being applied with minimal coordination. 

Thanks for sharing. I will close this thread now.

Regards,

David