DP83822I: COL behavior at reset deassert

Hi Go,

The COL line is driven low by the PHY in full duplex MII mode. 

Are you having some issue with data throughput? Or any other functional issue?

Thanks,

David

Hi, David

Thank you for your comment.

My customer has some trouble of changing PHY address.

 So I guessed that bootstrap voltage of COL got lower than Mode 4 range of Table 8-9. 4-Level Strap Voltage Ratios on D/S page48 

and caused this problem.

What is the trigger to drive COL low? I thought reset signal was the trigger , but it looks that COL start to turn to low before Reset signal reaches to its threshold...

Regards,

Go

Hello,

I work on the same team as David. He is OoO due to the Labor Day Holiday. Please expect a delay in his next correspondence. 

Sincerely,

Gerome

Hi, David

How’s it going?

Any advice would be very appreciated.

Thanks,

Go

Hi Go,

What is the expected PHY address? What PHY address is actually being seen? Are you able to read/write registers after using the actual PHY address?

Can you share the schematic also?

Thanks,

David

Hi, David

Thank you for your comment.

Customer's expected PHY address is 0x01(default).

But sometimes connect with 0x02 or 0x03 under customer's evaluation.

I'll ask for the schematic to our customer and will share it via private message.

Thanks,

Go

Hi Go, 

Okay, yes please share the schematic. I would like to see what else (if anything) is connected to the strap pins. 

Have you tested multiple boards? Is the behavior the same on all?

Thanks,

David

Hi, David

I sent you a private message with schematic on Sep 14th.

Did you have a chance to see it?

Thanks,

Go

Hi, David

Thank you for your reply.

The register value are as follows,

　ADDR = 0x0467 : (0x2001)

　ADDR = 0x0468 : (0x0000)

these are read under normal condition.

Customer said they can't access PHY under abnormal condition, so they can't read them.

Is there any other point we should check?

Thanks,

Go

Hi Go,

How do you know the PHY address sometimes connects as 0x2 or 0x3?

Another peculiar thing is that bit[1] of 0x467 is read as 1. This mode is reserved and should not be used. First, I would like to verify that the reads are being performed correctly. Note that register 0x467 is an extended register so you must use the procedure given in section 8.4.2.1 of the datasheet. Can you read other extended registers such as 0x421 = 0x0007?

Thanks,

David

Hi, David

I told the customer about  your comment( the procedure for reading extended register), and 

I got some feed back about read value of registers 0x467, 0x468 ,and 0x421 as follows,

Type:PHY_ADR(0x0467) : [0x2001]

Type:PHY_ADR(0x0421) : [0x784D]

Type:PHY_ADR(0x0468) : [0x0000]

 these are not expected value?

Thanks,

Go

Hi Go,

These are not expected values, no. I am expecting register 0x421 to read 0x0007. Can you please check the procedure used to read extended registers? Can you read any other extended registers correctly?

Thanks,

David

Hi, David

Thank you for your comment.

Let me confirm to the customer again.

Is there any other possible cause that unexpected register values were read except incorrect procedure?

Thanks

Go

Hi Go,

We may have gotten a little off topic. If the strap values are changing after each power up, the MAC is pulling the strap pins and affecting the latched values. The solution to this is to ensure the MAC pins are high-Z while the PHY is coming out of reset.   

I was recommending to read register 0x467 and 0x468 to confirm that strap values are changing, but the above is true regardless. Please ensure the MAC pins are high-Z while the PHY is booting up or coming out of reset. 

Thanks,

David

Hi,David

Thank you for your advice.

I got it, let me check it to the customer.

Generally, Are the MAC pins set to high-Z while the PHY is booting up or reset?

Or does it depend on customer's design?

Thanks,

Go

Hi, David

Thank you for your advice.

I confirmed again about  the MAC pins setting during the PHY is booting up or reset.

Customer said they set the MAC pins which are connected to PHY strap inputs as "input" during the PHY is booting up or reset.

so they consider the MAC pins are High-Z. Is customer's understanding correct?

Is there any good way to determine the MAC pins are properly Hi-Z?

Thanks,

Go

Hi Go,

Is this behavior seen on multiple boards?

Earlier you mentioned the PHY address "sometimes connect with 0x02 or 0x03 under customer's evaluation.". Can you let me know how this was known? Can they read/write by addressing PHY address 0x2 or 0x3 in the fail case?

Can you please check that the extended register access procedure in section 8.4.2.1 of the datasheet is being followed. Does the value of register 0x467, 0x468 change from power up to power up? Please power cycle the device at least 10 times and let me know if it is changing. 

Does issuing a pin reset after the failure case fix the issue?

Are there any other functional issues besides read/write not functioning occasionally?

Thanks,

David

Hi, David

I'm really sorry for the late reply.

As for your question, please refer to below.

Is this behavior seen on multiple boards?
→Yes. This issue has been occurring on multiple boards.

Earlier you mentioned the PHY address "sometimes connect with 0x02 or 0x03 under customer's evaluation.". Can you let me know how this was known? Can they read/write by addressing PHY address 0x2 or 0x3 in the fail case?
→In case they couldn't access expected PHY address(0x01), customer try to access other PHY address(0x02 to 0x32).
As a result of this procedure, got ACK from PHY address between 0x02 and 0x32.

Can you please check that the extended register access procedure in section 8.4.2.1 of the datasheet is being followed.
→The customer follows the procedure of 8.4.2.5 Read (No Post Increment) Operation

Does the value of register 0x467, 0x468 change from power up to power up? Please power cycle the device at least 10 times and let me know if it is changing.
→The customer checked the value of register 0x467, 0x468 and 0x421 10 times power-up cycle.
read value of each register are same.

ADR(0x0467) : [0x2001]
ADR(0x0421) : [0x784D]
ADR(0x0468) : [0x0000]

Does issuing a pin reset after the failure case fix the issue?
→Cases are different on each boards.
Case1 : once connect with unexpected PHY address(0x02 or 0x03), the PHY address they can access doesn't change after reset.

Case2: the PHY address they can access is one of 0x00 to 0x32, except 0x01, and changes every power-up cycle.

Case3: connect with unexpected PHY address very rarely (20 times out of 100,000times-reset).

Thanks,

Go

Hi Go,

Register 0x467 is showing that LED0 is strapped in mode 2 which is reserved and should not be used. It is also showing that RX_D0 strap is mode 3 which corresponds to PHY address of 16. Please check the voltage on these pins when the reset pin is de-asserted.

Register 0x421 is showing that VDDIO was detected as 2.5V. We can force the detection to 3.3V using register 0x41F bits[11:10]. Please try this and issue a soft reset afterwards 0x001F = 0x4000. 

Thanks,

David