DP83848I: EMI Issue

Hi Fabio,

Sure, I can have a look at the design. 

First, please let me know if you are disabling the CLKOUT pin of the PHY. This will be a source of 25Mhz if not disabled.

Thanks,

David

I have confirmed that Pin25 CLK_OUT is also floating.

Do they need to disable this in the software side?

Hello,

I work on the same team as David. He is OoO due to the Labor Day Holiday. Please expect a delay in his next correspondence. 

Sincerely,

Gerome

Is there any feedback?

Hello,

David is still OoO. Please expect a response by next Monday.

Sincerely,

Gerome

Hi David, Is there any suggestions to suppress the 25MHz?

Hi Fabio,

One possible source of noise is the MII traces. We can tell if this is the case by stopping the MII port switching from the PHY, by setting register 0x0 bit[10]. Can you perform another scan with this bit set and share the results?

I am checking for a way to disable the internal switching on the CLK_OUT pin. 

I was unable to open the layout files, can you share via Altium or pdf format?

Thanks,

David

Hi David,

The customer is trying to set the register.

They will perform another scan after some deeper investigation.

The layout is as below. 

Could you pls help to check it?

Thanks

P3-WIFI-V01_20230801.PcbDoc

Hi Fabio,

Sure I can have a look. Can you send a pdf copy of the schematic as well?

Thanks,

David

Hi David, whether this one is enough?

Hi Fabio,

I had a look at the schematic and layout and did not find anything glaring. To help isolate the issue can you help to conduct the following experiments:

1. With MII isolate enabled (register 0x0 bit[10] = 1). This will tell if the MII traces are playing a role.

2. With cable removed. This will tell if the cable is playing a role.

3. IEEE PWDN (register 0x0 bit[11])

Thanks,

David