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TCAN1145-Q1: Register configuration in Standby mode

Part Number: TCAN1145-Q1

Hey Expert,

There are some issues about the TCAN1145 while supporting customers. Could you help me with the following questions?

  • The section of 10.4.5.1 Selective Wake Mode notes that 'All Selective Wake registers must be written followed by a read to ensure they are programmed correctly
    for the proper frame detection and selective wake configuration. Once configured, the SWCFG bit should be set to 1'. I want to know What the Selective Wakeup Register refers to, and if the reading and writing of the selective wake registers can be verified in standby mode.  
  • The customer is currently configured for Selective Wake-up in Standby mode. The WKERR bit is always set when write 0x0 to 51h register. And the customer has turned off the SWE timer.  And the PWRON bit is always set when write 0x0 to 52h register. I want to know why the registers of 51h and 52h cannot be written successfully.  

Thanks for support!

Best Regards,

Chloe Liu

  • Chloe,

    I'd recommend the customer read this application note to get more detailed instructions and information on configuring and using selective wake.

    In order to clear interrupt flags, a 1 must be written to the specific bit and it will then clear as long as the interrupt condition is no longer present.

    Please let us know if there are any other questions from the customer.

    Regards,

    Eric Hackett