TCAN1044V: question about DTO

Lijia,

Thanks for reaching out, good question. When an error occurs, CAN controllers indicate this to the bus by deliberately transmitting 6 consecutive dominant ("0") bits on the bus to interrupt communication. These error frames can begin as soon as a node detects an error, including the transmitting node. One situation that could occur would be when the transmitting node detects an error that begins being signaled at the end of 5 consecutive dominant bits. This would require 6 more dominant bits to be sent, meaning 5 + 6 = 11 bits would need to be sent in a row.

You are correct that bit-stuffing causes CAN messages with 5 or more dominant "0" bits to have a recessive "1" bit stuffed into the data to prevent 6 consecutive dominants, but the exception is error frames, where this rule is deliberately violated in order to cause all nodes to interpret a communication error.

Best,

Danny