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SN65MLVD048: Split single-ended output from M-LVDS receiver

KB
Prodigy 170 points
Part Number: SN65MLVD048


I would like to split the single-ended output from the SN65MLVD048 part--one branch would go to some MMCX connectors that would go off the board (50 ohm circuit overall) and the other branch would go to a GPIO pin on an FPGA.  Assume we are using the interface at the max frequency of the receiver (250Mbps).  What is the optimal way to split this signal for the best signal integrity?

  • 0
    TI__Mastermind 25620 points

    Hello KB,

    From the output trace you can create a "Y" pattern (just split the trace into two), or you can place a via alongside the trace and use the top trace for the MMCX connector and the other trace for the GPIO pin. If timing/skew is a concern then the two traces need to length matched. 

    Regards,

    Josh

  • 0 in reply to Joshua Salinas
    Prodigy 170 points

    What about the effects of impedance mismatch?

  • 0 in reply to KB
    TI__Mastermind 25620 points

    Hello KB,

    In this case you will have 3 traces, one trace coming from the output and two traces branching to the MMCX connector and GPIO pin. Let’s say the same characteristic impedance (Zo) is used for all traces. The equivalent impedance where the trace splits will be the two traces in parallel.

    For example, if Zo = 50 Ω, then the equivalent impedance will be 25 Ω.

    To solve this mismatch each split trace will need to be double of Zo (2 x Zo). This makes the equivalent impedance equal to Zo. Lastly, a pull-down resistor equal to 2 x Zo is required to minimize any reflection issues.

    Regards,

    Josh