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SN65DSI86: MIPI Dual DSI interface 2@1920x1080 not working

Theresa Murdock
Prodigy 70 points
Part Number: SN65DSI86


We are using a Xilinx FPGA to generate two MIPI video streams, both of which go through their own Meticom MC20902 chip before going to the SN65DSI86 chip. We are using the TI spreadsheet to generate register settings for the SN65DSI86 and I've verified that the timing values in the registers are correct. We can see 3840x1080 Display Port video out of the SN65DSI86 on the external monitor with we enable the SN65DSI86 test pattern, and we can see single DSI 1920x1080 from the FPGA, through the SN65DSI86 to the monitor when the SN65DSI86 is configured for single DSI channel.

 

I'm getting CH A checksum errors (reg 0xF1 bit 2) when the single channel DSI interface is working, but the video looks fine on the monitor. We've also looked at the signals on a high speed oscilloscope and the signals, eye diagram, and timing all look very good. The left and right DSI channels are being generated by the same FPGA IP and are configured with the same timing.

 

In dual channel DSI mode (left/right), I'm getting checksum errors on both CH A and B (reg 0xF1 bit 2 and reg 0xF3 bit 2) and also getting Unexpected HSYNC (reg 0xF6 bit 1) and Data Underrun (reg 0xF6 bit 6). I also get intermittent Unexpected Pixel Data errors (reg 0xF6 bit 2), intermittent loss of DP Sync Lock errors (reg 0xF6.6 bit 6), and very intermittent Unexpected Data errors (reg 0xF6 bit 5).

 

The only things I changed to go from dual channel DSI model to single channel was to change register 0x10 from 0x80 to 0x20 and to change reg 0x94 from 0x80 or 0xE0 (I've used both) to 0x20. This tells me the DSI signals are most likely good and that the timing is correct.

 

Are there any other changes that need to be made to go from single DSI channel to dual DSI channel? What can cause dual DSI channels to not work when single DSI channel with the same signals do work? Does the SN65DSI86 have specific requirements for A and B input video stream synchronization?

 

FYI, I have confirmed that the display uses ASSR and fails if I set it for no ASSR, since that seems to come up in a lot of posts.

  • 0
    TI__Mastermind 43286 points

    Hey Theresa,

    when both channel A and B are driving your display, is the display working? If the display is working and you're getting the errors try resetting the error bits and see if they get set again.  

    If the display isn't working with channel A & B, can you send d over the register calculation spreadsheet with all the calculations you're using?

    To double check, please try recalculating the register values using the spreadsheet found in this E2E link: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers

  • 0 in reply to Vishesh Pithadiya
    TI__Guru**** 180041 points

    Hi,

    How are you configuring the MIPI source? When configured for dual DSI channels, the SN65DSI86 will use VSS, VSE, and HSS packets from SN65DSI86 channel A. The DSIx6 will use channel A events to recreate the same timings on the DisplayPort interface. The VSS, VSE, and HSS packets from channel B are used to internally align data on channel B to channel A.

    In LEFT/RIGHT mode, the left portion of the line is received on channel A, and the right portion of the line is received on channel B. The pixels received on channel B in LEFT/ RIGHT mode are buffered during the left-side transmission to DisplayPort, and begin transmission to DisplayPort when the left-side input buffer runs empty. The only requirement for LEFT/RIGHT mode is CHB_ACTIVE_LINE_LENGTH must be at least 1 pixel.

    Thanks

    David

  • 0
    Prodigy 70 points

    To answer Vishesh's question (sorry, I missed this email last week), we used the TI spreadsheet to generate the register values; the only difference is I’m setting registers 0x12 and 0x13 to our MIPI line rate divided by 10 (we’ve been experimenting with different line rates). When we disable the SN65DSI86 test pattern we do normally still get video on our display, but it’s black video and not the test pattern the FPGA is sending.

     To answer David's question, our MIPI is coming from an FPGA that’s using two sets of Xilinx MIPI DSI modules to generate the left/right video. Each video stream is configured the same with a resolution of 1920x1080 @ 60 Hz, and both MIPI streams are enabled one right after the other in software (left is enabled first). We originally had two different Xilinx Test Pattern Generators feeding each of the MIPI DSI modules independently, but after I submitted this post we switched to having a single Test Pattern Generator feeding both sets of MIPI DSI modules and we are now sometimes seeing both the left/right video channels on the monitor.

    With this version of the FPGA (common test pattern generator), when I disable the SN65DSI86 test pattern, I will usually get unexpected pixel data errors and loss of DP sync lock error (yes, I clear errors first to ensure these are ongoing errors). After a few seconds to a minute, those errors will clear and we’ll start getting the left/right video from the FPGA displayed on our external monitor. After a minute or so we’ll lose the test pattern, after a few seconds it will come back, and a few second later it will go away. We might get a couple cycles of that but eventually our FPGA test pattern will go away forever (and black video will be sent from the SN65DSI86 instead). Each time the video goes away we get a loss of DP sync lock error, then when video comes back that error is gone. By the time the FPGA video goes away forever we’ll usually have most of the following errors: loss of DP sync lock, unexpected pixel data, unexpected data, unexpected HSYNC, and occasionally unexpected VSYNC. We also get CHA and CHB checksum errors the entire time, but since we get FPGA video even when those errors are occurring they don’t seem to be causing any problems.

    Theresa

  • 0 in reply to Theresa Murdock
    TI__Mastermind 43286 points

    Hey Theresa,

    In my experience checksum errors are most likely due to signal integrity issues at the DSI input, and the errors seen in the 0xF6 registers are likely due to a timing issue.

    Could you send me the display panel spec you are using, and the register values you are using currently, so I can help debug?

    Also could you double check that the DSI signal seen by the SN65DSI86 is within spec?

  • 0 in reply to Vishesh Pithadiya
    TI__Mastermind 43286 points

    Hey Theresa,

    I'm going to close this thread due to inactivity.