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DS280MB810: BG_SEL_IPP and BG_SEL_IPH of Register 0x0F improve the Bit Error Rate of 25G SERDES

Kevin Huang8
Genius 4485 points
Part Number: DS280MB810

Hi Team,

Please help to clarify below issues :

We found that adjusting BG_SEL_IPP and BG_SEL_IPH of Register 0x0F can effectively improve the Bit Error Rate of 25G SERDES.
But we can't find any more explanation about this parameter.
We want to know:
1. What can be improved by adjusting these two parameters? (Jitter or signal integrity or ...?)
2. What are the side effects after adjustment?(Thermal or power consumption or ...?)
3. In addition, we also want to know, if we want to reduce the crosstalk between channels, what Register can be adjusted?


  • 0
    TI__Mastermind 36043 points

    Hi Kevin,

    1) Typically increasing these bias currents may increase the bandwidth of the part or adjust the shape of the CTLE curve.  This may explain your increase in BER.  What data rate is this application?  Is your transmission media constant in this application?  If BER is improved due to adjustment to CTLE curve, it's important to make sure that it will be improved across all your applications.

    2) There will be some increase in power. An increase in bandwidth may allow a little more Rj through the device as well.

    3 I'm not aware of any way to reduce crosstalk between channels by adjusting device parameters.  If it's possible to reduce slew rate, this might reduce cross talk.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Genius 4485 points

    Hi Drew,

    Is there any additional debug command that can bypass Boost Stage2 and Bypass Driver for testing?

    Kevin

  • 0 in reply to Kevin Huang8
    TI__Mastermind 36043 points

    Hi Kevin,

    No, there's not an internal signal chain that bypasses boost stage 2 or the driver.

    How is your system debug going?  Are you still running into BER issues?

    Thanks,
    Drew