TCAN4550EVM: TCAN4550-Q1 high and low temperature cycle test failure

Hi Imelda,

What temperatures are they testing at?  How are they controlling the temperature? Are they placing the entire EVM in a temperature chamber, or using forced air directed on the TCAN4550 IC?

What temperature is it failing?

Can you provide scope or logic analyzer plots of the SPI signals when it is working and not working?  You said that SPI has no data, but you also said they read the register and see LEX (I think you meant LEC) = 2, EP=1, EW=1.  So I'm confused how you read that if SPI wasn't working.

Regards,

Jonathan

I will try to explain,

we test at 85℃ for 1200H, when testing at 312H,The CAN message sent to TCAN4550 is normal, but the measurement of TCAN4550 is not interrupted, and SDO has no data.

MCU read the register and see LEC = 2, EP=1, EW=1,and unable to send CAN messages through TCAN4550,and SPI has data at this time（SCK,CS,SDI）.

Hi Jie,

A non-responsive SPI transaction is likely a clock related issue.  If the clock has stopped, or has been disrupted during the SPI transaction, the device won't  respond due to the lack of a clock to operate the digital core and output the data on the SDO line. 

It is possible the higher temperature shift has caused a shift in the load capacitance in the crystal oscillator circuit that could result in a larger peak-to-peak amplitude voltage (Vpp) in the waveform.  If the lowest peak level of the waveform drops lower than 150mV, there is a potential for the device to switch to a single-ended clock mode because there is a comparator used to check the OSC2 pin for a "grounded" pin at startup that has a detection threshold between 90mV and 150mV (typically 100mV). 

This detection comparator is not disabled after startup, so the crystal circuit needs to be optimized to prevent the OSC2 pin voltage from dropping below this level while oscillating.

Higher temperatures seem to cause a reduction in the parasitic capacitance and therefore a higher Drive Level in the crystal which produces a larger waveform.  The EVM was not specifically designed for or rated for temperature testing, and the crystal circuit may not be optimized for your 85C test conditions.  Component tolerances between the crystal, load capacitors, and the TCAN4550 may slightly change the voltage levels from board to board.

If this is the issue, I would recommend replacing the 0-ohm series resistor R30 on the EVM with a 50 to 100 ohm resistor.  This will reduce the current flowing to the crystal and lower the drive level preventing a mode switch.

You can find more information about the clock circuit in the TCAN455x Clock Optimization and Design Guidelines application note.

Can you try to replace this resistor and see if there is a change to the test results?

Regards,

Jonathan

Hi Nerger,

We know this issue,and I measured the crystal frequency deviation of TCAN4550 under high temperature, which is normal and the amplitude is greater than 150mV.

The crystal matching resistor we are currently using is 47R.So we think is not this issue

We have also encountered similar problems at room and high temperatures,could you help analyze other reasons ?

Hi Jie,

I am glad you are aware of the clock configuration requirements.  But I will need more information to help further. 

You have provided that the LEC = 2, which indicates there is a Form Error detected that means the device received a frame that has the wrong format.  You have also said that the EP (Error Passive) bits = 1 which indicates that either the Transmit or Receive Error Counter has exceeded a value of 127.  If the device is detecting Form Errors, these message frames could account for the error passive state, but I don't know what is causing the errors on the bus and whether they are coming from the TCAN4550, or another node on the bus.

Can you provide the device's Status and Interrupt and Error Counter Register values?

0x000C (Status)

0x0800 (Modes of Operation and Pin Configuration)

0x0820 (Interrupts)

0x0824 (MCAN Interrupts)

0x1018 (Control Register)

0x1040 (Error Counter Register)

0x1044 (Protocol Status Register)

If you can't read the SPI registers because there is no signal on SDO, then please provide the oscilloscope or logic analyzer plots showing the SPI communication failure.  Also monitor and let me know the value of the VSUP, VIO, and VCCOUT supply pins, as well as the Reset (RST) pin. 

The schematic image you shared does not have the Reset (RST) pin but calls pin 19 "nSTB".  I did not see any pullup or pulldown resistors on this net, but it should be LOW for normal operation.  If this net is pulled high, the device registers will be reset.

Regards,

Jonathan

Hi Nerger，

Can I understand in this way that because EP=1(either the Transmit or Receive Error Counter has exceeded a value of 127),our MCU is no longer able to send CAN messages through TCAN4550 and receive messages through it?

Our working state will continue to have message sending and receiving. We tested 312H and during this period, there may be error frames generated, while the counter is only 128, which is possible to reach the upper limit. When the upper limit is reached, TCAN4550 is unable to send and receive CAN messages anymore because it is in the EP=1 state?

Can we solve the problem of not being able to send and receive messages by exiting this state?

I will retrieve the register status you need after the next problem occurs.

thanks！

Hi Jie,

The TCAN4550 operated according to the ISO 11898-1:2015 CAN FD Standard.  The MCU can still transmit messages in the Error Passive state.  If the Transmit Error Counter (TEC) exceeds 255, the device will enter a Bus-Off (BO) condition and it will be disabled from participating in CAN bus communication. However the device should not enter a BO condition if the Receive Error Counter (REC) exceeds 255 because these errors were detected from message frames that were transmitted from another node on the CAN bus.

For your reference, the Error-active, Error-passive, and Bus-off states are defined in the ISO 11898-1:2015 standard as:

6.13 Error-active
An error-active node normally takes part in bus communication and sends an active error flag when an
error has been detected. The active error flag consists of 6 consecutive dominant bits and violates the
rule of bit-stuffing and all fixed formats appearing in a DF and RF (see 12.1.4.2).

6.14 Error-passive
An error-passive node sends no active error flag. It takes part in bus communication, but when an error
has been detected a passive error flag is sent. The passive error flag consists of 6 consecutive recessive
bits. After transmission, an error-passive node waits some additional time before initiating a further
transmission (see suspend transmission in 10.4.6.4 and 12.1.4.2).

6.15 Bus-off
A node is in the bus-off state when it is switched off from the bus due to a request of FCE. In the busoff
state, a node neither sends nor receives frames. In the bus-off state, a node does not send any
dominant bits.

If you are not seeing the BO=1, the device should be able to participate in CAN bus communication and transmit messages.  Can you confirm the value of the BO bit?  Also reading the error counter register will tell us how many REC and TEC errors there are so we can see the reason for why the device has entered the EP state and help us determine what may need to be improved.

If the device is not in a BO condition and it still is not able to communicate, there may be some other issue or fault with the device (voltage, clock, etc.) that is preventing it from working that may be reported in the status and interrupt registers I previously mentioned.

Regards,

Jonathan

Hi Jie,

To your question about can you exit the Error Passive state to solve the problem, you would need to completely reset and reconfigure the TCAN4550-Q1 in order to clear the error counters.  However, the CAN standard has generally defined the error counters to work by increasing the counters by 8 when an error frame is detected, and to decrease the error counters by 1 on a good message that did not contain an error. 

There are some conditions and exceptions for the transmit and receive counters, but this is the general principle.  Therefore, when an error occurs, the counters will be updated to reflect this error, but the counters should decrease with time with additional successful communication that doesn't contain errors.  If the error counters are increased faster than than they are decreased, the device will enter the Error Warning, and then the Error Passive states, before eventually entering a Bus Off state if the errors are coming from the messages that device is transmitting on the bus.

If there are enough errors on the CAN bus to cause a device to enter the EP state, resetting the device to clear the counters won't resolve the reason why the errors occurred on the bus.  This will only reset the error counters once they reach a certain level.

Regards,

Jonathan