Hello, does the 947 support the second clock for LVDS (usually pinned between D6+ and D7-) ? And if not, will displays with dual LVDS channels continue to work?
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Hello, does the 947 support the second clock for LVDS (usually pinned between D6+ and D7-) ? And if not, will displays with dual LVDS channels continue to work?
Hi Bruce,
The 947 can only accept one LVDS clock input. If you are operating the 947 in DUAL OLDI, both outputs will be timed off one clock input. What is the the customer's purpose of using the second LVDS clock? What configuration are they trying to achieve? The oLDI CLK is 1/2 the PCLK if using Dual oLDI. But if using single oLDI output, then oLDI CLK = PCLK.
Josh
Hi,
We're trying to resolve an image on a 1920x1080p display using dual OLDI. Without SerDes, the second image is achieved, but with an input into the 947 and output from 948, we're getting 4 images rather than one as seen in the fist image.
Hi Bruce,
I highly doubt this is a SerDes related problem, seems more like a timing issue or a panel issue. To clarify the issue, could you provide the interface timing spec and configuration selection on 947 and 948?
Best,
Josh
Hi Josh,
We're using default settings on both eval boards. So far, we've tested 2 different displays which work over a direct connection to the video source, but have the same problem where 4 repeat images appear after connecting SerDes. I've attached images of the current settings of the eval boards.
Hi Bruce,
On 947, could you confirm that OLDI interface? Because it looks using dual-pixel OLDI interface, but MODE_SEL0 is set as single. Please double check for me. Even it is not working after matching mode selections, we can first start with 948 PatGen, verify the target timing and no system level display-side issues, then work back towards SER side by first doing SER PG, then finally end to end.
Best,
Josh
The 947 switch was placed incorrectly. However, after fixing it, the same issue is still appearing. With the 948 patgen, the initial External clock setting results in a similar problem as before, where 4 images appear on the screen. Changing this to an internal, 1080p 60Hz setting produces the expected image. The same issue appears on the 947 patgen, where the initial settings seem to be causing the same 4 image problem, which is then fixed by going to an internal clock.
The below settings created a correct display.
The below settings created a problematic display
Hi Bruce,
As it was mentioned before, I believe that this is not a SerDes related problem, seems more like a timing issue or a panel issue. You are sending different resolution, timing, and PCLK between normal and abnormal. Note that it shows the abnormal video signal if you are not sending the appropriate timing. Could you share the desired timing?
Best,
Josh
Hi Josh,
We are trying to use this screen, I have attached the datasheet as well. One thing that is interesting is that the image appears fine without connecting through SerDes, directly from source to display directly over LVDS.
Hi Bruce,
If it is not working with external, please note that you need to check the source as PCLK, jitter, etc. as external timing is from the source to serializer.
Best,
Josh
Hi Bruce,
Internal timing or Internal timing with External Clock are enabled by the control registers in the datasheet. Also, please refer to the app note: Exploring the Int Test Pattern Generation Feature of FPDLink III IVI Devices (SNLA132).
Best,
Josh