DS90UB941AS-Q1: DS90UB941AS-Q1: split mode support

soc(QCM6125) output 3840*1200@30fps size image

Hi,

I will check and get back to you within 1-2 business days.

Regards,
Fadi A.

Hey Hong,

What is the issue here, are you seeing  black screen on both displays? Did you try testing with Patgen first?

hongwu shi said:

{0x0c, 0x40, 0x04}, //DSI/DPHY port0
{0x0c, 0x41, 0x05},
{0x0c, 0x42, 0x2e}, //dsi clock 438,

What is your superframe PCLK frequency?

hongwu shi said:

{0x0c, 0x41, 0x20},
{0x0c, 0x42, 0x6f},

Are you intending to disable "DSI_SYNC_PULSES" here? This will inform the DS90UB941AS-Q1 receiver that it should expect only horizontal/
vertical sync start packets, and enable override controls for HSYNC and VSYNC signal generation

hongwu shi said:

{0x0c, 0x1e, 0x01}, //port0
{0x0c, 0x03, 0x9a}, //pass_through
{0x0c, 0x1e, 0x02}, //port1
{0x0c, 0x03, 0x9a}, //pass_through
{0x2c, 0x1e, 0x09}, //port0 panel backlight

Here is how you can configure I2C 

board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
board.WriteI2C(Ser_addr,0x07,0x2C) #0x07,0x2C Des0 IDX (7-bit address)
board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c Des0 Alias
board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0

board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02,
board.WriteI2C(Ser_addr,0x07,0x30) #0x07,0x30 Des1 IDX (7-bit address)
board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E Des1 Alias
board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04

hongwu shi said:

{0x30, 0x34, 0x19}, //Forced Mode: Single link, secondary input
{0x30, 0x1e, 0x09}, //port0 panel backlight
{0x0c, 0x01, 0x00}, //enable dsi

Why are you using secondary input on Des side? Is Dout1 of 941AS physically connected to RIN1 of Des ?

Regards,
Fadi A.

1.What is the issue here, are you seeing  black screen on both displays? Did you try testing with Patgen first?

yes,all the screens are black.I try testing with Patgen  but  the screen is still black.

my script pattern configuration is shown below.I try let screen on port0 to display.please check it.

adb shell i2cset -fy 1 0x0c 0x01 0x08 b
adb shell i2cset -fy 1 0x0c 0x01 0x02 b

adb shell i2cset -fy 1 0x0c 0x5b 0x01 b
adb shell i2cset -fy 1 0x0c 0x1e 0x01 b
adb shell i2cset -fy 1 0x0c 0x03 0x9a b
adb shell i2cset -fy 1 0x2c 0x1e 0x09 b

adb shell i2cset -fy 1 0x0c 0x01 0x00 b
adb shell i2cset -fy 1 0x0c 0x06 0x01 b
adb shell i2cset -fy 1 0x0c 0x56 0x02 b    


adb shell i2cset -fy 1 0x0c 0x40 0x04 b
adb shell i2cset -fy 1 0x0c 0x41 0x21 b
adb shell i2cset -fy 1 0x0c 0x42 0x60 b
adb shell i2cset -fy 1 0x0c 0x40 0x04 b
adb shell i2cset -fy 1 0x0c 0x41 0x05 b
adb shell i2cset -fy 1 0x0c 0x42 0x32 b


adb shell i2cset -fy 1 0x0c 0x66 0x03 b
adb shell i2cset -fy 1 0x0c 0x67 0x1F b   //set N=31

adb shell i2cset -fy 1 0x0c 0x66 0x04 b
adb shell i2cset -fy 1 0x0c 0x67 0x20 b

adb shell i2cset -fy 1 0x0c 0x66 0x05 b
adb shell i2cset -fy 1 0x0c 0x67 0xB8 b

adb shell i2cset -fy 1 0x0c 0x66 0x06 b
adb shell i2cset -fy 1 0x0c 0x67 0x4D b

adb shell i2cset -fy 1 0x0c 0x66 0x07 b
adb shell i2cset -fy 1 0x0c 0x67 0x80 b

adb shell i2cset -fy 1 0x0c 0x66 0x08 b
adb shell i2cset -fy 1 0x0c 0x67 0x07 b

adb shell i2cset -fy 1 0x0c 0x66 0x09 b
adb shell i2cset -fy 1 0x0c 0x67 0x4b b


adb shell i2cset -fy 1 0x0c 0x66 0x0a b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x66 0x0b b
adb shell i2cset -fy 1 0x0c 0x67 0x04 b

adb shell i2cset -fy 1 0x0c 0x66 0x0c b
adb shell i2cset -fy 1 0x0c 0x67 0x0C b

adb shell i2cset -fy 1 0x0c 0x66 0x0d b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x66 0x0e b
adb shell i2cset -fy 1 0x0c 0x67 0x0F b

adb shell i2cset -fy 1 0x0c 0x66 0x1a b
adb shell i2cset -fy 1 0x0c 0x67 0x06 b  //set M=6

adb shell i2cset -fy 1 0x0c 0x65 0x05 b
adb shell i2cset -fy 1 0x0c 0x64 0x53 b

2.What is your superframe PCLK frequency?

4000*1243*30=149,160,000

3.Are you intending to disable "DSI_SYNC_PULSES" here? This will inform the DS90UB941AS-Q1 receiver that it should expect only horizontal/
vertical sync start packets, and enable override controls for HSYNC and VSYNC signal generation

Whether the register retains its default value?

4.Why are you using secondary input on Des side? Is Dout1 of 941AS physically connected to RIN1 of Des ?

 Dout1 of 941AS physically connected to RIN1 of Des.Use a separate i2c for control.

Hey Hong,

Here is a script with patgen using your timing ... the pclk is hard to match yours since our internal clock is based on a 200Mhz clock so the closest I could get it is 66.6Mhz ... it works on my setup can you try on yours?

import time
Ser_addr = 0x18

time.sleep(0.5)
board.WriteI2C(Ser_addr,0x01,0x08) # Reset
board.WriteI2C(Ser_addr,0x01,0x02) # Reset

time.sleep(0.5)
board.WriteI2C(Ser_addr,0x5B,0x07) #Set 941AS to Splitter mode

board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
board.WriteI2C(Ser_addr,0x66,0x1A)
board.WriteI2C(Ser_addr,0x67,0x01) #M=1
board.WriteI2C(Ser_addr,0x66,0x03)
board.WriteI2C(Ser_addr,0x67,0x03) #N=3

board.WriteI2C(Ser_addr,0x66,0x04)
board.WriteI2C(Ser_addr,0x67,0xDB) #least 8 bit of Total Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x05)
board.WriteI2C(Ser_addr,0x67,0x04) #Least 4 bit TV + Most 4 bit TH
board.WriteI2C(Ser_addr,0x66,0x06)
board.WriteI2C(Ser_addr,0x67,0x41) #Most 8 bit of Total Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x07)
board.WriteI2C(Ser_addr,0x67,0xB0) #least 8 bit of active Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x08)
board.WriteI2C(Ser_addr,0x67,0x04) #Least 4 bit AV + Most 4 bit AH
board.WriteI2C(Ser_addr,0x66,0x09)
board.WriteI2C(Ser_addr,0x67,0x3C) #Most 8 bit of active Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x0A)
board.WriteI2C(Ser_addr,0x67,0x0A) #Horizontal Sync Width
board.WriteI2C(Ser_addr,0x66,0x0B)
board.WriteI2C(Ser_addr,0x67,0x04) #Vertical Sync Width
board.WriteI2C(Ser_addr,0x66,0x0C)
board.WriteI2C(Ser_addr,0x67,0x06) #Horizontal back porch
board.WriteI2C(Ser_addr,0x66,0x0D)
board.WriteI2C(Ser_addr,0x67,0x13) #Vertical back porch
board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars

board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1
board.WriteI2C(Ser_addr,0x66,0x1A)
board.WriteI2C(Ser_addr,0x67,0x01) #M=1
board.WriteI2C(Ser_addr,0x66,0x03)
board.WriteI2C(Ser_addr,0x67,0x03) #N=3

board.WriteI2C(Ser_addr,0x66,0x04)
board.WriteI2C(Ser_addr,0x67,0xDB) #least 8 bit of Total Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x05)
board.WriteI2C(Ser_addr,0x67,0x04) #Least 4 bit TV + Most 4 bit TH
board.WriteI2C(Ser_addr,0x66,0x06)
board.WriteI2C(Ser_addr,0x67,0x41) #Most 8 bit of Total Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x07)
board.WriteI2C(Ser_addr,0x67,0xB0) #least 8 bit of active Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x08)
board.WriteI2C(Ser_addr,0x67,0x04) #Least 4 bit AV + Most 4 bit AH
board.WriteI2C(Ser_addr,0x66,0x09)
board.WriteI2C(Ser_addr,0x67,0x3C) #Most 8 bit of active Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x0A)
board.WriteI2C(Ser_addr,0x67,0x0A) #Horizontal Sync Width
board.WriteI2C(Ser_addr,0x66,0x0B)
board.WriteI2C(Ser_addr,0x67,0x04) #Vertical Sync Width
board.WriteI2C(Ser_addr,0x66,0x0C)
board.WriteI2C(Ser_addr,0x67,0x06) #Horizontal back porch
board.WriteI2C(Ser_addr,0x66,0x0D)
board.WriteI2C(Ser_addr,0x67,0x13) #Vertical back porch
board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars


board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c
board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0


board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02, 
board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E
board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04

board.WriteI2C(Ser_addr,0x01,0x00) # Reset

hongwu shi said:

4000*1243*30=149,160,000

If your PCLK is 149.16 Mhz then your DSI CLK is running at 447.48 Mhz and given that you are using 4 DSI lanes, your TSKIP should  be 0x30.

board.WriteI2C(UB941AS,0x40,0x04) # TSKIP_CNT
board.WriteI2C(UB941AS,0x41,0x05) # TSKIP_CNT
board.WriteI2C(UB941AS,0x42,0x30) # TSKIP_CNT

hongwu shi said:

Whether the register retains its default value?

This depends on how your SoC is sending data - Please check DSI bring up guide. 

DSI Bringup Guide.pdf

hongwu shi said:

 Dout1 of 941AS physically connected to RIN1 of Des.Use a separate i2c for control.

Is there a reason you're not using the primary input RIN0?

If you are using RIN1 then you'd need to force that in Register 0x34 locally on 948 side otherwise it won't work.

Basically you need to write 0x19 to register 0x34 to enable RIN1. You need to do this with a local I2C connection to the 948 side otherwise it won't work.

Regards,
Fadi A.

1.Here is a script with patgen using your timing ... the pclk is hard to match yours since our internal clock is based on a 200Mhz clock so the closest I could get it is 66.6Mhz ... it works on my setup can you try on yours?

I found that the timing in your configuration is 1200*960, you should reverse the width and height, and this screen is dual link lvds so you need to multiply the width by 2.

The following is the script after I modify the panel timing(1920*1200) according to you,but still black screen.please check.

adb shell i2cset -fy 1 0x0c 0x01 0x08 b
adb shell i2cset -fy 1 0x0c 0x01 0x02 b

adb shell i2cset -fy 1 0x0c 0x5b 0x07 b
adb shell i2cset -fy 1 0x0c 0x1e 0x01 b

adb shell i2cset -fy 1 0x0c 0x66 0x1A b
adb shell i2cset -fy 1 0x0c 0x67 0x01 b
adb shell i2cset -fy 1 0x0c 0x66 0x03 b
adb shell i2cset -fy 1 0x0c 0x67 0x03 b

adb shell i2cset -fy 1 0x0c 0x66 0x04 b
adb shell i2cset -fy 1 0x0c 0x67 0x20 b

adb shell i2cset -fy 1 0x0c 0x66 0x05 b
adb shell i2cset -fy 1 0x0c 0x67 0xB8 b

adb shell i2cset -fy 1 0x0c 0x66 0x06 b
adb shell i2cset -fy 1 0x0c 0x67 0x4D b

adb shell i2cset -fy 1 0x0c 0x66 0x07 b
adb shell i2cset -fy 1 0x0c 0x67 0x80 b

adb shell i2cset -fy 1 0x0c 0x66 0x08 b
adb shell i2cset -fy 1 0x0c 0x67 0x07 b

adb shell i2cset -fy 1 0x0c 0x66 0x09 b
adb shell i2cset -fy 1 0x0c 0x67 0x4b b


adb shell i2cset -fy 1 0x0c 0x66 0x0a b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x66 0x0b b
adb shell i2cset -fy 1 0x0c 0x67 0x04 b

adb shell i2cset -fy 1 0x0c 0x66 0x0c b
adb shell i2cset -fy 1 0x0c 0x67 0x0C b

adb shell i2cset -fy 1 0x0c 0x66 0x0d b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x65 0x04 b
adb shell i2cset -fy 1 0x0c 0x64 0x15 b

adb shell i2cset -fy 1 0x0c 0x1e 0x02 b

adb shell i2cset -fy 1 0x0c 0x66 0x1A b
adb shell i2cset -fy 1 0x0c 0x67 0x01 b
adb shell i2cset -fy 1 0x0c 0x66 0x03 b
adb shell i2cset -fy 1 0x0c 0x67 0x03 b

adb shell i2cset -fy 1 0x0c 0x66 0x04 b
adb shell i2cset -fy 1 0x0c 0x67 0x20 b

adb shell i2cset -fy 1 0x0c 0x66 0x05 b
adb shell i2cset -fy 1 0x0c 0x67 0xB8 b

adb shell i2cset -fy 1 0x0c 0x66 0x06 b
adb shell i2cset -fy 1 0x0c 0x67 0x4D b

adb shell i2cset -fy 1 0x0c 0x66 0x07 b
adb shell i2cset -fy 1 0x0c 0x67 0x80 b

adb shell i2cset -fy 1 0x0c 0x66 0x08 b
adb shell i2cset -fy 1 0x0c 0x67 0x07 b

adb shell i2cset -fy 1 0x0c 0x66 0x09 b
adb shell i2cset -fy 1 0x0c 0x67 0x4b b


adb shell i2cset -fy 1 0x0c 0x66 0x0a b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x66 0x0b b
adb shell i2cset -fy 1 0x0c 0x67 0x04 b

adb shell i2cset -fy 1 0x0c 0x66 0x0c b
adb shell i2cset -fy 1 0x0c 0x67 0x0C b

adb shell i2cset -fy 1 0x0c 0x66 0x0d b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x65 0x04 b
adb shell i2cset -fy 1 0x0c 0x64 0x15 b

adb shell i2cset -fy 1 0x0c 0x1e 0x01 b
adb shell i2cset -fy 1 0x0c 0x07 0x58 b
adb shell i2cset -fy 1 0x0c 0x08 0x5c b
adb shell i2cset -fy 1 0x0c 0x03 0x9a b
adb shell i2cset -fy 1 0x2c 0x1e 0x09 b

adb shell i2cset -fy 1 0x0c 0x1e 0x02 b
adb shell i2cset -fy 1 0x0c 0x07 0x58 b
adb shell i2cset -fy 1 0x0c 0x08 0x5e b
adb shell i2cset -fy 1 0x0c 0x03 0x9a b
adb shell i2cset -fy 2 0x30 0x34 0x19 b
adb shell i2cset -fy 2 0x30 0x1e 0x09 b

adb shell i2cset -fy 1 0x0c 0x01 0x00 b

Hey Hong,

Could you look at the DSI debug guide I sent above and mark down which step in the flow is passing/failing for you so we could take a step back to have better assessment on this debug.

Regards,
Fadi A.

Could you look at the DSI debug guide I sent above and mark down which step in the flow is passing/failing for you so we could take a step back to have better assessment on this debug.

the fisrst step

Hi Hongwu, 

Has 948 PG been successfully programmed and output already? This will ensure everything is working using the targeting timing and no system level issues (backlight off, etc). 

Are you able to attach a USB2ANY to the system to use the PatGen tab in ALP? This will make things much easier to dial in the PG timing if that is what is incorrect.

Regards, 

Logan

Has 948 PG been successfully programmed and output already? This will ensure everything is working using the targeting timing and no system level issues (backlight off, etc). 

Haven't tried 948 PG yet.941 PG,the backlight is on.Can you give me a 948 PG script?

Are you able to attach a USB2ANY to the system to use the PatGen tab in ALP? This will make things much easier to dial in the PG timing if that is what is incorrect.

I don't have USB2ANY.

Hi Hongwu

I notice a couple issues with your script for PG above. 

First, your PG script will only output from port 1 as currently written. This is okay for now, I would advise we first verify Port 0 display first with correct PG, then we can move on from there.

Your script sets a PCLK of 154.8MHz, but this too high for single port. Instead, 30Hz has to be used (per above), so this PCLK needs divided by 2. Instead I recommend to use M=3 instead for a PCLK of 77.

0x0E=0xF is turning off Horizontal Sync. Instead, I recommend to use 0x0E=0x3 (if HS/VS needs inverted), otherwise 0x00.

Here is output from ALP tab tool for PG, this can be used to generate the list of register values.

Register Data Name
0x0000 0x00 PGRS
0x0001 0x00 PGGS
0x0002 0x00 PGBS
0x0003 0x1F PGCDC1
0x0004 0x20 PGTFS1
0x0005 0xB8 PGTFS2
0x0006 0x4D PCTFS3
0x0007 0x80 PGAFS1
0x0008 0x07 PGAFS2
0x0009 0x4B PGAFS3
0x000A 0x14 PGHSW
0x000B 0x04 PGVSW
0x000C 0x0C PGHBP
0x000D 0x14 PGVBP
0x000E 0x00 PBSC -> Update based on polarities
0x001A 0x03 PGCDC2

Regards, 

Logan

•  I tweaked the script like you suggestedm,but still black screen.

adb shell i2cset -fy 1 0x0c 0x01 0x08 b
adb shell i2cset -fy 1 0x0c 0x01 0x02 b

adb shell i2cset -fy 1 0x0c 0x5b 0x01 b //set port0
adb shell i2cset -fy 1 0x0c 0x1e 0x01 b
adb shell i2cset -fy 1 0x0c 0x03 0x9a b
adb shell i2cset -fy 1 0x2c 0x1e 0x09 b

adb shell i2cset -fy 1 0x0c 0x01 0x00 b
adb shell i2cset -fy 1 0x0c 0x06 0x01 b
adb shell i2cset -fy 1 0x0c 0x56 0x02 b    


adb shell i2cset -fy 1 0x0c 0x40 0x04 b
adb shell i2cset -fy 1 0x0c 0x41 0x21 b
adb shell i2cset -fy 1 0x0c 0x42 0x60 b
adb shell i2cset -fy 1 0x0c 0x40 0x04 b
adb shell i2cset -fy 1 0x0c 0x41 0x05 b
adb shell i2cset -fy 1 0x0c 0x42 0x32 b


adb shell i2cset -fy 1 0x0c 0x66 0x03 b
adb shell i2cset -fy 1 0x0c 0x67 0x1F b  //set N=31

adb shell i2cset -fy 1 0x0c 0x66 0x04 b
adb shell i2cset -fy 1 0x0c 0x67 0x20 b

adb shell i2cset -fy 1 0x0c 0x66 0x05 b
adb shell i2cset -fy 1 0x0c 0x67 0xB8 b

adb shell i2cset -fy 1 0x0c 0x66 0x06 b
adb shell i2cset -fy 1 0x0c 0x67 0x4D b

adb shell i2cset -fy 1 0x0c 0x66 0x07 b
adb shell i2cset -fy 1 0x0c 0x67 0x80 b

adb shell i2cset -fy 1 0x0c 0x66 0x08 b
adb shell i2cset -fy 1 0x0c 0x67 0x07 b

adb shell i2cset -fy 1 0x0c 0x66 0x09 b
adb shell i2cset -fy 1 0x0c 0x67 0x4b b


adb shell i2cset -fy 1 0x0c 0x66 0x0a b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x66 0x0b b
adb shell i2cset -fy 1 0x0c 0x67 0x04 b

adb shell i2cset -fy 1 0x0c 0x66 0x0c b
adb shell i2cset -fy 1 0x0c 0x67 0x0C b

adb shell i2cset -fy 1 0x0c 0x66 0x0d b
adb shell i2cset -fy 1 0x0c 0x67 0x14 b

adb shell i2cset -fy 1 0x0c 0x66 0x0e b
adb shell i2cset -fy 1 0x0c 0x67 0x00 b

adb shell i2cset -fy 1 0x0c 0x66 0x1a b
adb shell i2cset -fy 1 0x0c 0x67 0x03 b  //set M=3

adb shell i2cset -fy 1 0x0c 0x65 0x05 b
adb shell i2cset -fy 1 0x0c 0x64 0x53 b

Hi Hongwu, 

Was the backlight command activated per the original script?

{0x2c, 0x1e, 0x09}, //port0 panel backlight

The following script can be used to ensure the correct active resolution is making it to the DES. 

import time
UB947 = 0x18
UB948 = 0x58

board.WriteI2C(UB948,0x68,0x19) # H active High monitor
time.sleep(0.1) # Critical delay! Needed for proper operation!
for x in range(0,100):
	board.WriteI2C(UB948,0x68,0x19) # Need to write this register again after the delay
	Hhigh = board.ReadI2C(UB948, 0x69, 1)
	board.WriteI2C(UB948,0x68,0x09) # H active Low monitor
	Hlow = board.ReadI2C(UB948, 0x69, 1)
	board.WriteI2C(UB948,0x68,0x39) # V active High monitor
	Vhigh = board.ReadI2C(UB948, 0x69, 1)
	board.WriteI2C(UB948,0x68,0x29) # V active Low monitor
	Vlow = board.ReadI2C(UB948, 0x69, 1)
	mask = int('00111111',2)
	hlowmask = Hlow & mask
	hhighmask = Hhigh & mask
	vlowmask = Vlow & mask
	vhighmask = Vhigh & mask
	hhighmask = hhighmask << 6
	vhighmask = vhighmask << 6
	Hactive = hhighmask | hlowmask
	Vactive = vhighmask | vlowmask
	print "Detected Resolution = ",Hactive,"x",Vactive

board.WriteI2C(UB948,0x68,0x00) # Disable PGENBIST

Regards, 

Logan

Was the backlight command activated per the original script?

{0x2c, 0x1e, 0x09}, //port0 panel backlight

I didn't forget to set it

The following script can be used to ensure the correct active resolution is making it to the DES. 

board.WriteI2C(UB948,0x68,0x19) # H active High monitor
time.sleep(0.1) # Critical delay! Needed for proper operation!
for x in range(0,100):
board.WriteI2C(UB948,0x68,0x19) # Need to write this register again after the delay
Hhigh = board.ReadI2C(UB948, 0x69, 1)->>0x9E
board.WriteI2C(UB948,0x68,0x09) # H active Low monitor
Hlow = board.ReadI2C(UB948, 0x69, 1)->>0x80
board.WriteI2C(UB948,0x68,0x39) # V active High monitor
Vhigh = board.ReadI2C(UB948, 0x69, 1)->>0x92
board.WriteI2C(UB948,0x68,0x29) # V active Low monitor
Vlow = board.ReadI2C(UB948, 0x69, 1)->>0xb0
mask = int('00111111',2)
hlowmask = Hlow & mask
hhighmask = Hhigh & mask
vlowmask = Vlow & mask
vhighmask = Vhigh & mask
hhighmask = hhighmask << 6
vhighmask = vhighmask << 6
Hactive = hhighmask | hlowmask
Vactive = vhighmask | vlowmask
print "Detected Resolution = ",Hactive,"x",Vactive

board.WriteI2C(UB948,0x68,0x00) # Disable PGENBIST

• I calculated the resolution to be 1920*1200,is correct.But black screen, backlight only.

We measured and compared the waveforms of FPD Link III between this device and other project devices. They roughly look the same. How can we tell whether the FPD Link III signal is valid? Are there any examples or standard waveforms? The difference we can see is that there is a difference in the timing of the LVDS signal output by the UB948. Is this the root cause of the no display on the screen of the device?

Below are lvds data lane waveforms that can be displayed normally on other items.

Below is the lvds data lane waveform currently being debugged

Hi Hongwu, 

FPD-Link is confirmed not to be the problem here if resolution check came back correct.

The resolution check verifies that the 941 is properly sending the video timing to DES, and DES is successfully receiving. This seems like an issue with the underlying timing or something on the display side. 

You will need to verify the display side to better understand if there is a video timing parameter issue or something else system level (panel power, panel enable, etc). Ultimately, if there is a video parameter issue (blanking, refresh rate, etc); you will need to identify this in the PG script and adjust accordingly. 

If you have other successful display bring-ups with this panel, maybe those can be leveraged for the correct display/video settings.

Regards, 

Logan

The resolution check verifies that the 941 is properly sending the video timing to DES, and DES is successfully receiving.

Whether I still need to try 948 PG?

• The screen backlight is good, the power supply is good.All I can think of is panel timing,but hactive and vactive is correct. And how do I check the panel blank?That's the only doubt I have

Hi Hongwu,

Since the doubt regarding the information making it to the DES is removed, I think this step probably isn't needed.

Is this display brought up in any other system/program? Is this the first time the display is brought up with FPD-Link?

Panel blanking will need to be checked with the display module vendor or display system supplier. Maybe one of the above blanking parameters is being misinterpreted (HS included in HFP, etc).

Regards,

Logan

I'll grab a 941PG lvds waveform later.

Dear Logan,

Below is the lvds waveform diagram of 948 output that I captured.Please help to check whether it is correct.

Hi Hongwu, 

The OLDI CLK and output look valid. This looks more so to be potentially a video timing issue (video blanking, polarity, etc) as indicated before. Maybe there is a PCLK, Htotal, Vtotal, polarity, or other video timing parameter being violated as currently programmed into PG of 941. The probed OLDI signals and resolution detection readback prove that 948 appears to be operating correctly.

Are you sure the display panel can accept 30fps? It directly specifies 60Hz in datasheet table. 

hongwu shi said:

2.

Can you comment on the below:

Logan Cummins said:

Panel blanking will need to be checked with the display module vendor or display system supplier. Maybe one of the above blanking parameters is being misinterpreted (HS included in HFP, etc).

Logan Cummins said:

Is this display brought up in any other system/program? Is this the first time the display is brought up with FPD-Link?

Regards, 

Logan

Do not use 941PG, use SOC source, 948 0x64 set 0x53 can be displayed (only set 0x53 or 0x13 can be displayed) but 941 0x64 set 0x53 can not be displayed, what is the problem?

948 on port1 can now display the soc output data source.However, 948 on port0 is still not displayed.Do not use 941PG, use SOC source, 948 on port0 0x64 set 0x53 can be displayed (only set 0x53 or 0x13 can be displayed) but 941 0x64 set 0x53 can not be displayed, what is the problem?

I don't fully understand that the issue is here. If you enable patgen from 948 that means you are ignoring the SoC video stream. 

941 is configured with split mode.Now 948 on port1 can display SOC video strem but 948 on port0 can't display.

Set port0 PATGEN_ASCRL = 1,Only pure blue and white can be displayed on panel0.

Set port1 PATGEN_ASCRL = 1,All colors can be displayed on panel1.

Hi Hongwu, 

This is very odd. Typically with our devices you either get patgen working for all patterns or it doesn't work at all. We have never seen it work on some patterns and doesn't on others. What is the difference between the 1st the 2nd displays are they identical , same TCON , etc. ?

Have you tried testing local patgen from 948 side, does that also show issue with port0 and no issue with port1?

Regards,
Fadi A.

This is very odd. Typically with our devices you either get patgen working for all patterns or it doesn't work at all. We have never seen it work on some patterns and doesn't on others. What is the difference between the 1st the 2nd displays are they identical , same TCON , etc. ?

Both panels are identical.

Have you tried testing local patgen from 948 side, does that also show issue with port0 and no issue with port1?

Yes,patgen from 948 side,that also show issue with port0 and no issue with port1.

Hi Hongwu, 

hongwu shi said:

Yes,patgen from 948 side,that also show issue with port0 and no issue with port1.

Ok so the issue is in the output side of the data path, it's somewhere between the 948 LVDS output  -> TCON -> panel. It's possible that this display has some issue, do you have a different display to try on port0?

If you swap port0 display with port1 display do you still see the same issue? I'm trying to see if the issue follows Port0 display when you plug it into port1 cable. 

Regards,
Fadi A.