SN65DSI86EVM: DP panel not getting video frames

Hello Vishesh,

Thanks for the quick response.

I have gone through the Excel provided in the above ticket. but as we are using Qualcomm_noASSR mode, I have checked the tab, but few of the registers are as #NAME, and a few writable values are as only addresses, not values. so I am not able to understand. Please, can you help us understand that?

Attaching the screen shot for your reference

Hey Jigar,

Ill have a look at the calculator to make sure everything is good. Can you send me all the data you inputted to the calculator so I can try to recreate the problem? I'm not entirely sure why the calculator is having issues. 

While I do that, there is a black screen debugging guide I'll link below that covers the most common issues, try seeing if that can help.

Guide: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide?tisearch=e2e-sitesearch&keymatch=sn65dsi86#

Hello Vishesh,

Please find the timing which we are setting on DP panel 

Will go through provided thread and debug the status register and update you in case if I found any thing 

Regards,

Hey Jigar,

I've noticed that the Qualcomm_noASSR section is a bit buggy which we will work on fixing, but while that is happening, the values found on the Main_Inputs_Page in the EDID Registers Table are all there and accurate. Try seeing if those values work.

Hello Vishesh,

Is there any update on the Qucalcomm_noASSR section?

Regards

Hello  Vishesh,

I have tried to set the register as per suggested way, but still not getting any output on DP panel.

And I have gone through the suggested thread and below is the status of few of the registers

Reg       - value
0xF0        0x02

0xF1        0x03

0xF5       0x20

0xF8       0x01

Can you help me to understand the error status, as we are getting in above error. and suggest me where should i debug.
Please let me know incase of any other information required.

Regards

Based off of the registers provided it seems that link training is performed successfully, but there is an issue with the PLL lock as well as loss of data. More details can be found in section 8.1 of the SN65DSI86 datasheet.

Could you send me more data regarding the clock speed used at the source and sink?

Hello Vishesh,

Please find the i2c dump output when EVM is connected.

Please let me know if you need more information.

Hey Jigar,

Let me have a look and get back to you :)

Hello Vishesh,

On Linux machine with spreadsheet, we are able to generate proper DSI sequence command from the provided Excel.
and we have added command to DSI ON command. and able to read it back from the I2C. But we are not getting any output on the connected DP display.

Please have a find the register output when we write the SN65DSI86 register with the DSI. 

Can you suggest us the issue where do we need to validate the connection side or any other issue might be causing this issue? can you help us to resolve this issue.

Regards

I'm doing more research into what the issue is, but while I'm doing that please have a look here.

I'm still working on narrowing down this issue, as if you are using the calculator the register values should be correct.  This might be an ASSR issue as well as timing. Can you double check your CLK timings, and follow the steps in this debugging guide. https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide?tisearch=e2e-sitesearch&keymatch=sn65dsi86#

Based off of the data you have sent, we know that the issues are the PLL lock, checksum error, and ECC error. Can you send me the spec of the DSI source being used? Also have you tried editing the ASSR settings as seen in the link above?

Hello Vishesh,

Yes, I do follow the link and configure the ASSR register, but still getting the same issue.

Regards

Hello Vishesh,

I have tried with lower resolution 1280X720 with single DSI, and able to get output on the DP panel.

But when I am trying to derive  register settings for 1920X1080 mode with single DSI, getting issue with the "Min DSI A clk rate"  and "Min DSI B clk rate"  shell of the excel. 

but when I set "# of DSI B lanes" to 1 or higher till 4 then getting DSI A/B clk value. and if I set the value "# of DSI B lanes" to 0 then getting like "CLK TO FAST" issue.

So do we need to configure 2 DSI for 1920X1080? can you conform that?

This should get rid of the clock too fast issue.

Thanks for the quick replay, Fast clock issue resolve with this, 

But when I am configuring 2880X1440@90 FPS, getting flickering on the screen. attaching the video for your reference.  can you help me to identify where do i need to look? JFI 2880X1440@60 working fine. Also attaching the setting register page from the excel for your reference.

Hey Jigar,

are you able to probe the DSI inputs?

This is again most likely a timing issue, and I now want to make sure that the Hsync and Vsync are correct. Also if you arent already try using REFCLK, as this will clean up the clock signal and help eliminate potential issues.