• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 261 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIC12400-Q1: Test Issue

Lanxi Li
Expert 6795 points
Part Number: TIC12400-Q1
Other Parts Discussed in Thread: TIC12400,

Hello team,

We use IN0 and IN1 of TIC12400 as CAN interrupt wake-up detection. Due to the leakage current in INx and the large external resistance added to IN0 and IN1, when the MCU goes to sleep and TIC12400 is in polling detection mode, IN0 and IN1 appear last time. A periodic voltage, the maximum voltage is about 1.3V. The TIC12400 register sets the comparison voltage of these two pins to 2V. It obviously does not reach the trigger limit, but the INT PIN will detect a low level. May I ask why this phenomenon occurs?

Add:
Set the comparison voltage to 2.7V: INT Pin will detect low level
Set the comparison voltage to 3V: INT Pin remains high
Set the comparison voltage to 4V: INT Pin remains high

Best regards,

Lanxi

  • 0
    TI__Mastermind 33030 points

    Hi Lanxi,

    I see you have created two separate E2E threads on this same issue, so I will be closing the second thread (link) and responding to both threads in this one.

    The datasheet specifies a maximum leakage current of up to 110uA, but your stated observation of 24uA in the other thread is consistent with measurements and calculations I have made.  You can find an explanation and overview in this thread. (Link)

     It is recommended to place a capacitor on each INx pin that is used for several reasons.  Our ESD ratings of +/-8kV are based on having a 15nF capacitor, 10 ohm series resistor on the pin which creates a filter.  Without the capacitor, the device may not meet this rating. 

    However, this capacitor will also absorb and filter a large portion of the leakage current and reduce the amplitude of the observed voltage spike during the active measurement phase of the polling cycle when the MUX is active for that channel.

    Please review the other thread I have linked to for an explanation and consider adding a capacitor to the pin as a recommended solution to this issue.

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    TI__Mastermind 33030 points

    Hi Lanxi,

    I'm re-posting the information from your other thread

    Hello team,

    We adjusted the wetting current of IN0/IN1 to 1mA and found that there is still leakage current. By measuring the voltage at WAKE of 0.192V, we estimated that the leakage current is about 24uA. If the leakage current here is too high, it will affect the system function.

    1. If IN0/IN1 is connected to an external signal with a pull-up source (open drain structure), can the wetting current be adjusted to 1mA or higher? Are there any hidden dangers?
    2. If the wetting current can be adjusted, please provide the leakage current spec when wetting current = 1mA or higher.

    Best regards,

    Lanxi

    1. It is not recommended to source a positive value of wetting current onto a signal that has a pullup resistor to a supply voltage.  This will create multiple current paths and could cause damage if current flowed between the two separate supply sources.

    If the wetting current is coming from an external pullup resistor to a voltage source then the device could be used in a current sink configuration.

    However, I believe that your desire is to use the TIC12400-Q1 with 0-mA and simply monitor the voltage level on the signal.  Is that correct?

    2. The leakage current is in the analog MUX circuit that connects the INx pin to the ADC or Comparator for measurement, and it is essentially the same for all wetting current levels.  It is usually not an issue when there is a positive or non-zero amount of wetting current enabled.

    The recommendation is to add a filter capacitor on the pin, or you can reduce the values of the resistors.  This is essentially an Ohm's law (V = I * R) situation where the leakage current coming from the VS supply voltage results in a voltage drop across the large resistor values on the INx pin.  The capacitor creates a lower impedance path to GND for this leakage current.

    Regards,

    Jonathan