DS90UR241: I/O extender

Chen Alex1

Part Number: DS90UR241

hi Sir

Due to insufficient FPGA IO, we currently want to use a set of outputs and inputs to drive more than two sets of DS90UR241/DS90UR124 respectively. The schematic diagram is as follows:

over 2 years ago

0 Clemens Ladisch over 2 years ago

Guru 317750 points

You can use more buffers like this.

What is your question?

0 Chen Alex1 over 2 years ago in reply to Clemens Ladisch

Genius 3925 points

have any time delay issue?

0 Clemens Ladisch over 2 years ago in reply to Chen Alex1

Guru 317750 points

At 43 MHz, the length of a bit is 23 ns, so the propagation delay of the buffers is probably not large enough to introduce problems. But to minimize skew, run the clock signal through the same buffer.

(The '240 is an inverter; the '244 is a buffer.)

Interface

Interface forum

DS90UR241: I/O extender