Other Parts Discussed in Thread: USB-2-MDIO
Hi,
We have designed a new board that uses DP83822IF for Ethernet PHY. We have followed all the layout and design guidelines. We have compared our design with the DP83822 Eval board as well. After power up the eval board auto-negotiates to 100Mbps, but our board attempts 4-5 times and then locks to 10Mbps. This of course occurs after power up and before the MAC even starts communicating with the PHY and initializes it.
Q1- Have you seen this issue in the past with other board implementations? What area is typically the issue?
Q2- (P/N) We are using the F version instead of the base version. F is supposed to support fiber as well as copper. We use copper at this point. Is there something special about F?
Q3- (Power up sequence) The datasheet says it is preferred to have VDDA come up after VDDIO. Our implementation, same as the eval board, both rails come up together. Is that OK?
Q4- (Bootstrap) We believe we have the correct setting?
Thank you