DP83867IR: Device tree configuration for DP83867IRRGZ phy under &gem

Hi Sujan,

I believe you have to set reg = <0x1> for gem3, assuming the phy address is 1.

Attached is the dts documentation available on open source kernel, please let me know if this helps.
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/devicetree/bindings/net/ti,dp83867.yaml?h=v5.10.197

Regards,
Rahul

Thank you Rahul for responding, 

I tried setting the reg = <0x1> for gem3 but it did not work.
I got the same error message at u-boot.

Any other suggestions ?
Should i add a mdio node within gem node and lastly phy node ?

Regards,

Sujan 

Hi Sujan,

Yes, you would be needing an MDC, MDIO pins definition in the device tree.

SoC will try to access the PHY address <0x1> of the PHY using MDC/ MDIO interface. If that interface is not defined, then PHY cannot be accessed and hence cannot be found.

Regards,
Rahul

Hi Rahul,

I tried this config, but got the same error on u-boot 
And now the kernel wont start & is stuck in Starting Kernel...

&gem1 {
   phy-handle = <&phy0>;
   xlnx,has-mdio = <0x1>;
   local-mac-address = [00 01 02 03 04 05];
   phy-mode = "rgmii-id";
   xlnx,ptp-enet-clock = <0x0>;

   mdio {
      phy0: phy0@2 {
         device_type = "ethernet-phy";
         compatible = "ti,dp83867", "ethernet-phy-ieee802.3-c22";
         reg = <2>;
         ti,fifo-depth = <0x1>;
         ti,dp83867-rxctrl-strap-quirk = <1>;
      };
   };
};


&gem3 {
   phy-handle = <&phy1>;
   xlnx,has-mdio = <0x1>;
   local-mac-address = [1A 2B 3C 4D 5E 6F];
   phy-mode = "rgmii-id";
   xlnx,ptp-enet-clock = <0x0>;
   mdio {
      phy1: phy1@4 {
         device_type = "ethernet-phy";
         compatible = "ti,dp83867", "ethernet-phy-ieee802.3-c22";
         reg = <4>;
         ti,fifo-depth = <0x1>;
         ti,dp83867-rxctrl-strap-quirk = <1>;
      };
   };
};

Any idea what I'm doing wrong.

Regards,

Sujan

Hi Sujan,

Let me try to find a .dts file and share it with you.

Regards,
Rahul

Thank you Rahul, that would be of great help.

Regards,
Sujan

Sure.

Hi Sujan,

Please find attached .dts file for one of the TI processor board.

k3_j721e_common_proc_board.dts

Regards,
Rahul

Hi Rahul,

I tried this config now using davinci_mdio as in the one you sent:

    /include/ "system-conf.dtsi"
    #include <dt-bindings/net/ti-dp83867.h>
     
    &gem3 {
            status = "okay";
            phy-mode = "rgmii-id";
            phy-handle = <&phy0>;
            davinci_mdio {
                    phy0: ethernet-phy@0 {
                            reg = <0>;
                            ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                            ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                    };
            };
    };

The kernel starts now, but the u-boot still shows PHY not detected. 
Could this be a hardware issue, how can i test that the chip is communicating with PL or not ??

Thanks & Regards,
Sujan

Hi Sujan,

To verify if the PHY is working. We could measure the CLK_OUT pin of the PHY to verify if you can measure the clock there.

This can indicate that PHY is alive.

Next we would need to access registers using MDC/ MDIO. If this communication is not working, using a logic analyzer we can measure the MDC/ MDIO lines and test the functionality.

We also have a troubleshooting guide available for DP83867, please use this for PHY level debugs:
https://www.ti.com/lit/an/snla246b/snla246b.pdf?ts=1697134631871&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards,
Rahul

Hi Rahul,

We probed the clk_out  found that its not producing any output.
Also probed the reset_n & found out that its high, as it should be since its active low.

Does this mean PHY is dead ?

Regards,
Sujan

Hi Sujan,

With Reset high or low, you should be able to see CLK_OUT if the PHY is being supplied input clock through XI.

Regards,
Rahul

Hi Rahul,

We are using a crystal connected to XI & XO(25MHz). But we are unable to see any clock on these pins.
We also tried to toggle the reset low to high, but still we are unable to get any clock input or outputs on the pins.

Regards,
Sujan

Hi Sujan,

XI is input to the PHY, if that clock is not available the PHY will not be functional.

Regards,
Rahul

Hi Rahul,

Update - We checked the oscillator and it seems to be working.
Our initial deductions was that, the PHY is not exciting the oscillator so it's not producing the XI input.

So, we checked the register values through MDIO to check if they are same as given in the Datasheet for DP83867
We followed this guide https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/145031176/Reading+PHY+registers+over+MDIO+via+the+PHY+Management+GEM+Register

Our PHY is bootstrapped to phy address 0x0c, so we followed the same steps except we used GEM1 address.
But we noticed the 4th hexa number is being incremented by 1 for every register.

root@dual_dma_intr_v1:~# devmem 0xff0c0000 32 0x00000010
root@dual_dma_intr_v1:~# devmem 0xff0c0034 32 0x66020000
root@dual_dma_intr_v1:~# devmem 0xff0c0034
0x6603FFFF

Notice that register i was trying to read from was 0x6602, but the output was of 0x6603.

Also the value for that reg BMCR should have been 1140 and not FFFF.

Why is this happening ?

Thanks & Regards,
Sujan

Hi Sujan,

Is the device tree issue resolved ? Are you facing register access issues currently ?

Wanted to confirm if the driver bring-up is successful ?

Regards,
Rahul

Hi Rahul,

No I'm still not sure about the device tree.

Since we are still not able to produce clk_out from PHY, we still have to resolve that before we can proceed with device tree debugging.

Yes we are facing register access issues as I had mentioned earlier.

Regards,
Sujan

Hi Sujan,

We have a troubleshooting guide for DP83867:
https://www.ti.com/lit/an/snla246b/snla246b.pdf?ts=1699477193988&ref_url=https%253A%252F%252Fwww.google.com%252F

This might help resolve the PHY related issue.

Regards,
Rahul

Hi Rahul, 

We are following that guide already.

But as I asked earlier, while reading reg 0x66020000, its returning 0x6603xxxx values.

Could you please tell me why its returning 0x6603 instead of 0x6602 ?

Regards,
Sujan

Hi Sujan,

Can you please help clarify which register you are reading ?
The following is the returning value of which register ?

Sujan S M said:

Could you please tell me why its returning 0x6603 instead of 0x6602 ?

Sujan S M said:

Also the value for that reg BMCR should have been 1140 and not FFFF.

I understand from this above comment, that you are accessing the BMCR which is Reg 0000h, and you are reading the value FFFFh.

This clearly indicates that MDC/ MDIO read operation is not happening properly.

If you refer to figure 8-9 in the datasheet:

https://www.ti.com/lit/ds/symlink/dp83867ir.pdf?ts=1699564678799&ref_url=https%253A%252F%252Fwww.google.com%252F

The MDIO line could be high and that is the reason for all FFFFh values.

Do you have a logic analyzer, can you capture an MDC/MDIO read or write operation and share ?

Also, if you are using Linux can you use phytool to read or write the registers ? here is an FAQ: 

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1164499/faq-how-to-read-and-write-ethernet-phy-registers-using-a-linux-terminal?tisearch=e2e-sitesearch&keymatch=phytool#

Regards,
Rahul