DS90UB933-Q1: DS90UB933-Q1

Hello Wei,

1. In the schematic, how did your team determine the inductors and ferrite beads used?
   1. The design doesn't seem to match the PoC solutions given in our TI documents. It resembles the example PoC networks that are given in the TI App Note SNLA224, but there are difference parts used. 
   2. For any PoC network, the customer needs to verify that each inductor/ferrite bead component they are using in the PoC network must have a saturation current rating that is greater than the expected current draw through the network. And that each component is also able to maintain its characteristics under extreme temperature and current load conditions.
   3. Customers should also simulate the impedance through the PoC network and check to see if the impedance is roughly greater than 1-kOhms over the operating frequency range of the FPD-Link devices. Higher impedance through the PoC network correlates to lower loss on the high-speed channel that is carrying video data. For the 933 devices, the operating range is roughly 1MHz - 1GHz.
   4. In addition, if you have an FAE or TSR from TI that is supporting your company, then you can ask them to request for our Channel Specifications design document, which includes Return Loss and Insertion Loss parameters that your PCB design should meet.
   5. We expect customers to verify that the high-speed channels they design have been verified to have minimal Return Loss, Insertion Loss, cross-talk, etc... (either through simulations or measurements on physical PCB).
2. The 3D pictures for the Top and Bottom layers are a little confusing, since you're showing the exact same image in both cases. Here is my feedback, based on the images given. Please let me know if I misinterpreted the images.
   1. It seems the 933 chip and the COAX connector are on the same layer.
   2. The routing of the DOUT+ traces goes from the Top Layer (933 -> C93) to the Bottom Layer through vias.
   3. The PoC network touches the DOUT+ trace in the Bottom Layer.
      1. Make sure that 50-Ohms (+/-10%) single-ended impedance is maintained both on the high-speed DOUT+ trace and the PCB traces within the PoC network.
      2. Use anti-pads (GND cut-outs), GND reference vias, and careful impedance calculations to make sure that tightly controlled 50-Ohms impedance is maintained. Reason is that each inductor in the PoC network can only block a limited frequency range. That means there is a small portion of the AC signal on the DOUT+ trace that will travel past the first and second inductor in the PoC network. Make sure to maintain 50-Ohms impedance, so that there are not additional reflections on the DOUT+ trace, which can add to the Return Loss.
      3. Make sure there is a continuous GND reference plane underneath the PoC and DOUT+ traces for impedance control and to also isolate the signal from other signals.
      4. Choose a PCB trace width on the DOUT+ and PoC network traces that is wide enough to carry the expected current load, without heating up the traces too much.
   4. I can't tell if the COAX connector is through-hole or surface mount, but make sure that there is minimal connector stub when routing the DOUT+ trace to the data pin of the COAX connector.

Best,

Justin Phan

Hello,Justin

     Thanks  for your reply.

    1.The inductors and ferrite beads from my colleagues，It's my first  using DS90UB933.

    a. After reading a lot of TI documents  SNLA224, SNLU210B, ZHCU283A and datasheet, there are still many doubts about which type inductors and ferrite to use.Which one should I refer to?

   b. Verify the POC network's inductor/ferrite bead component is difficult for me,because there's no relevant euqipment or verification methods ,so I want to know which one is the best to refer to.So far, We don't have any TI's FAE support except you.

    2. I’m sorry about that I uploaded the wrong 3D  Image.

    3D top

   3D bottom

a. It seems the 933 chip and the COAX connector are on the same layer.

----yes

b .The routing of the DOUT+ traces goes from the Top Layer (933 -> C93) to the Bottom Layer through vias.

---yes

d. It's  surface mount connector.

3.Please help to see which of the following two methods is better.

AA：

BB：

Bests.

Wei Long

Hello Wei,

1. We are currently planning on making the FPD3 datasheets to be a little clearer on our requirements. But let me try to provide additional clarification first. If there is any confusion, let me know.
2. Our serializer (933) will generate a Forward Channel signal (~1GHz) and send it to the connected deserializer across PCB traces and a cable. The deserializer will send a Back Channel signal (~1MHz) to the connected serializer over the same channel. In order for our devices to properly communicate with each other, there must not be too must Insertion Loss and Return Loss on the high-speed channel (PCB+Cable+PCB).
3. We've defined the maximum amount of Return Loss and Insertion Loss that can appear on the Total Channel (PCB+Cable+PCB). before our devices are unable to properly communicate with each other.
   1. We are planning on updating the datasheets to reflect this requirement in the future, but this information was already updated in the 953/954 datasheets. You can reference these tables below. Note that you only need to meet the IL/RL limit lines for the frequency range of (1MHz - 1GHz) for the 933 device.
   2. 
   3. 
   4. Table 7-6 from the 960 datasheet shows the limits for Return Loss and Insertion Loss across the Total Channel (Serializer PCB+Cable+Deserializer PCB).
      1. This is the requirement for the entire system (under max temperature conditions and under current load conditions).
      2. The PCB and cable all contribute to the loss across the entire high-speed channel.
   5. Table 8-3 from the 960 datasheet shows the recommended Return Loss and Insertion Loss limits for the individual PCB high-speed traces. In this case, the DOUT+ trace on your 933 camera module. We recommend designers confirm that the Insertion Loss and Return Loss of the PCB traces meet these limits, since it will make it easier to meet the required Total Channel requirements. But you also need to check the IL/RL characteristics of the cable being used in the system. If the cable has low loss, then you can afford more loss on your PCB design, in order to meet the Total Channel requirements. If your PCB has too much loss, then you need to use a cable that has lower loss, such that the total loss over the entire channel meets our requirements.
4. When you connect a PoC network onto the high-speed DOUT+/RIN+ traces, then that circuit will add more loss to your PCB budget. In order to minimize loss on your PCB, you need to be careful when designing your PoC network.
   1. App Note SNLA224 basically explains the following:
   2. Inductors have a Self-Resonant Frequency (SRF), which means each part has a specific frequency where the impedance is at its peak. PoC networks are generally composed of multiple inductors in series. The purpose is to provide high impedance (>1-kOhms) over the entire operating frequency range (1MHz - 1GHz) of the high-speed channel it is attached to, in order to clearly filter-out the AC and DC signals that are on the high-speed channel. Higher impedance typically correlates to lower loss on the Total Channel and it makes it easier to meet our Total Channel requirements limits.
   3. But the bottom line is that the Insertion Loss and Return Loss (between the Serializer and Deserializer) across the Total Channel must be within the limits.
   4. Also note that inductors lose their characteristics if a high enough DC current is sent through them. There is a Saturation Current specification for each inductor part that you use in your system. In power applications, you need to be careful and make sure that your serializer camera module only draws current that is below the saturation current spec in the inductor parts you've chosen.
   5. Also keep in mind the temperature rating of the inductors used. We expect that inductor characteristics are affected by higher temperatures and we expect more loss on the channel at extreme temperatures.
   6. All of these factors need to be considered when designing a PoC network and using it in a system. We typically recommend customers simulate the IL/RL across the high-speed channel (with the PoC network attached) and make sure the IL/RL limits are met across the operating frequency. And on the test board, place the system under extreme temperature and current load conditions, and then measure the loss across the channel and confirm it meets our channel requirements.

For your layout question, it seems AA is better, but its a bit hard to tell with the provided images. The main thing I'm noticing involves the through-hole COAX connector. If the COAX connector is through-hole, then then the DOUT+ signal should meet the connector at the end of the pin, to minimize connector stub.

Having a large stub will result in more reflections on the high-speed channel. Based on the pictures, it seems the connector and 933 chip are on opposite layers in AA, but they are on the same layer in BB. But it's still a little bit hard to tell in the pictures that were provided.

And it is okay to add a via, so that you can attach the PoC network to the DOUT+ trace. However, you need to make sure that 50-Ohms (+/-10%) single-ended impedance is maintained on the DOUT+ trace and the PoC network traces. And to add GND reference vias as well. This is something you should check with your fab house.

Best,

Justin Phan