DP83849IF: Auto-negotiation Time Out

Please tell me one more thing.
Is it okay to remove C88 from the EVM circuit below?

https://www.ti.com/jp/lit/df/snlr002/snlr002.pdf

(P4)

We checked the circuit diagram because the link up of the customer's system was not completed normally. I am asking this question because the capacitor at the relevant location was OPEN.

Hiroshi

Hi Hiroshi,

user5163865 said:

I think there is an algorithm that sets a timeout on the MAC side during auto-negotiation, and if it doesn't go well, restarts and repeats this, but there doesn't seem to be any regulation for this time itself.
What timeout period does TI recommend we set?

This depends on the customer's design and needs. In section 5.2.6 of the datasheet, it mentions that parallel detection and autonegotiation take around 2-3 seconds to complete so I would recommend around that time. 

user5163865 said:

Is it okay to remove C88 from the EVM circuit below?

This part is one of our older devices, so I'm not as familiar with the design guidelines. Could you ask the customer to try populating the capacitor?

What do you mean when you say the customer's system was not completed normally?

Best regards,

Melissa

HI Melissa-san,

Thank you for your support.

    >What do you mean when you say the customer's system was not completed normally?

According to information from customers, the following symptoms are occurring:

1. When power is applied, the opposite port does not recognize a link, and the defective port repeats link recognition and non-link recognition.
2. After some time passes, link recognition is completed, but link recognition takes longer than usual.
3. Compared to other normal ports, link recognition takes about 2 to 60 seconds.
4. The problem occurs only in link recognition immediately after startup, and it works normally after link recognition is completed.

Differences in symptoms by lot
　Check the link recognition status with the LED LINK port of the PHY IC.
　The IC with lot number "01A22EW" has 43 pins, and the IC with lot number "9AAYR8W" has 19 pins.
　The IC with lot number "01A22EW" has an event occurring in the communication port using pins 23, 24, 26, and 27.
　The IC with lot number "9AAYR8W" has an event occurring in the communication port using pins 35, 36, 38, and 39.
　If you connect the above pins of "01A22EW" and "9AAYR8W", the event will occur with a high probability, but it will not occur 100%. In the case of a 　combination of a good IC and a bad IC, the frequency of occurrence decreases.

　The defective IC was inspected by X-rays, but no damage inside the IC could be confirmed.

Additional questions
I would like to know if something like this has happened in the past.

Best regards,
Hiroshi

Hi Hiroshi,

I have a few clarifying questions:

• Is this board custom or TI Evm? Are the power feedback pins populated (refer to the section 8.5 POWER FEEDBACK CIRCUIT of the datasheet)
• What is the link partner? Another DP83849IF?
• Does this issue occur every time? On every PHY?

Please try disabling autonegotiation and forcing the speed selection in register 0x0 (BMCR) and observe how long it takes for the PHY to link up. Note you will have to do this on the link partner aswell.

I'm not sure if something like this has happened in the past with the DP83849IF but link issues are common with our PHYs.

Best regards,

Melissa

HI Melissa-san,

Customer boards are user custom.
The link partner is also the same DP83849IF.

The occurrence frequency is high with the lot combinations of "01A22EW" and "9AAYR8W", but it does not occur 100% of the time.
In the case of a combination of a good IC and a bad IC, the frequency of occurrence decreases.

I'll come back to this thread once I get the results of selecting the speed with auto-negotiation OFF.

Best regards,

Hiroshi

Hi Hiroshi-san,

I will await your test results.

Best regards,

Melissa