DP83822IF: Packet loss (~2%) in MII back-to-back media converter application

Hi Jean-Francois,

I'm a little confused on how the DP83822s are connected to each other, could you provide a block diagram of your 1st and 2nd design, including their link partners?

There were some instances where customers were using a faulty cable, cause some packet loss. Could you try switching out the cable? 

I also want to narrow down where the issue is, could you start by try reading register 0x15 on all the PHYs in the setup and see if it increases over time?

Best regards,

Melissa

Hello Melissa,
Find attached a schematic snippet of how both PHYs are connected together.

We do not have access to the MDIO bus on this card since it's a hard-wired, 100Mbps full duplex media converter application. Thus I cannot read the register @ address 0x15, but my guess is that would the RX_ER counter register.

Our setup is : 

PCIe MAC i210IT <-> PCB CU MDI <-> DP83822IF CU <-> MII <-> DP83822IF FX <-> PCB FX MDI <-> FX transceiver

The DP83822IF CU is configured as such:
Forced 100Base-TX, force full duplex, no MDIX, no autonegotiation, MII 25MHz

The DP83822IF FX is configured as such:
Forced 100Base-FX, force full duplex, no MDIX, no autonegotiation, MII 25MHz, SD_EN enabled, FX_EN enabled

Is this configuration (MII media converter) supported by the DP83822IF? I have seen instances where TI PHY could only work in such configuration in RGMII or RMII, but not in MII. 

A colleague of mine previously asked this question in TI e2e forums, and was told that yes a back-2-back media converter was possible with the DP83822IF, but without mentionning if it was possible in MII, RMII or RGMII.

e2e.ti.com/.../dp83822if-question-concerning-media-dependant-interface-options-for-phy-dp83822if 

Thank you and will wait for your input on this matter. Thanks for the quick feedback!

Hi Jean-Francois,

Thanks for providing your setup. This configuration should work with MII. 

• Did you try different cables to see if these affected packet loss at all?
• What kinds of cables are you using to connect between the boards?
• Can you go through your layout and complete this checklist: https://www.ti.com/lit/an/snla387/snla387.pdf?ts=1697050382815 (especially the section of MDI and MII traces)

Not having access to the registers will make the debug process more difficult since we can use the registers to verify certain functionalities. You might be able to access them if you get an MSP430 EVM and connect it to the MDIO/MDC lines through some soldering/rework.

Best regards,

Melissa

Hi Melissa,

As said previously, yes I have tried various optical cables, from brand new to existing ones used on other setups. This does not affect packet loss, which stays in the range of 2-3%.

Between the fiber transceiver and an off-the-shelf media converter, we use a standard ST or LC cable (we have both variants on our board). Same issue with either ST or LC. From the media converter, a standard RJ45 cable to the link partner that is used to issue the pings.

I could monitor the RX_ER line and see if it is toggled when I get a packet lost. I could also validate that a ping in the other direction (from our PCIe MAC to link partner) produces the same amount of packet loss. Right now I only tested from the link partner to our PCIe MAC.

But as said, I get stable link-up. Packet loss is sporadic (sometimes, more than 200-300 packet sent without issue when suddenly a packet is lost). It is not due to the fiber optical power since the signal detect input is stable and remains above the Vih(min) threshold at all times during operation.

I might also try to rework the board to set it up in RMII with a 50MHz clock to see if that could resolve the issue. Our previous design usign a PHY from another vendo (now EoL) used MII without issues but as said, I've read on the forum that media converter application with other TI PHYs was prohibited, and was prefered in RMII configuration.

Let me know if you can provide further assistance on this issue otherwise I will do additional testing on the prototype and come back with more data.

Best regards,

Jean-Francois Bilodeau, Eng.

Hi Jean Francois,

Apologies, I was mistaken. You can connect the PHY's MII to another processor's MII interface, but I do not believe you can do a back to back configuration like the one above.

Both TX_CLKs are being supplied to each other at the same time, which is what may be causing your 2-3% packet loss.

We suggest using RMII repeater mode instead. You can read more about how to configure the 822 in RMII repeater mode here:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1276229/faq-dp83822i-how-to-use-rmii-repeater-mode-in-dp83822?tisearch=e2e-sitesearch&keymatch=rmii#

Best regards,

Melsisa

Hi Melissa,

Thank you for your response.

Quick questions in order to prepare this test:

1) In this case, the RMII "Master" would be the one that is interfaced to the MAC through MDI, or the one interfaced to the fiber transceiver (DP83822IF CU would be the master PHY, and DP83822IF FX would be the slave PHY) ? I assume the master would be the CU phy

2) What should I do with unused pins for RMII? (TX_CLK, RX_CLK, TXD2, TXD3, RXD2, RXD3) ? Leave them floating?

3) The master PHY will automatically output a 50MHz clock on RXD3 based on HW strapping, which should then be connected to the XI input of the slave PHY, correct?

4) The strapping for the XI input shall be as shown below, M being master, S being slave, correct?

Thank you and I'll try to test this as soon as I have your valued feedback.

Also in this connectivity scheme, when the FX PHY fiber is disconnected, how is the far end fault propagated to the CU PHY? Since the CU PHY provides the clock to the FX PHY, what mechanism is put in place to make sure they both stay synchronized?