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SN65LVDS116: Termination scheme for the SN65LVDS116 and SN65LVDS105

Alex LeBlanc
Prodigy 90 points
Part Number: SN65LVDS116
Other Parts Discussed in Thread: SN65LVDS105,

I have a design where I plan on generating a reference clock using a 64MHz CMOS oscillator, which I then bring to a SN65LVDS105 (CMOS to 4x LVDS). Three of the SN65LVDS105's outputs then go to three SN65LVDS116, to create a total of 48 LVDS clocks. These 48 LVDS clocks go to 48 PCIe-type of connectors (so board-to-board, no cabling), which may or not be inserted. 

I want to make sure I properly terminate my receivers, but it's unclear from the datasheet what external components are suggested. I can't even figure out if the SN65LVDS116 receiver has internal termination or not (Figure 12 seems to suggest that it's internal, but the "equivalent input and output schematic diagrams" seems to suggest that it's not).

Could you please provide some guidance as to what should be on my LVDS lines between the SN65LVDS105 and my SN65LVDS116, as well as between the SN65LVDS116 and the receiver on the daughter board?

  • AC coupling capacitors? If so, what's the optimal location for these (near the driver, near the receiver, near connector on the motherboard, near the connector on the daughter board)?
  • DC biasing resistors?  
  • Common mode choke (e.g. DLW21SZ900HQ2L or similar)? Where's the optimal place to put this at? 
  • Series resistors at driver?
  • Termination scheme? E.g. just 100ohm between, or 50 and 50 with cap to GND?

I've seen several app notes that show the use of different schemes (such as SLAA840), but I'd like to know which setup would be recommended for this application. 

Note that the daughter board's receiver needs an external termination resistor and 100nF capacitors:




  • +1
    TI__Genius 10850 points

    Hello Alex,

    Thanks for reaching out and yes we can help here.

    First, the SN65LVDS116 does not have an internal termination. Figure 12 refers to a Fail-Safe feature in the LVDS116. This means when the inputs experience an open-circuit event (0V at the differential inputs), the output will go into a Logic High state.

    For your questions:

    Alex LeBlanc said:
    AC coupling capacitors? If so, what's the optimal location for these (near the driver, near the receiver, near connector on the motherboard, near the connector on the daughter board)?

    Placing the capacitor near the driver is fine.

    Alex LeBlanc said:
    DC biasing resistors?  

    Pull-up of 10 kΩ and pull-down of  5.7 kΩ

    Alex LeBlanc said:
    Common mode choke (e.g. DLW21SZ900HQ2L or similar)? Where's the optimal place to put this at? 

    These will go in between the AC capacitor and DC biasing circuit

    Alex LeBlanc said:
    Series resistors at driver?

    Not needed unless you need to adjust your characteristic impedance

    Alex LeBlanc said:
    Termination scheme? E.g. just 100ohm between, or 50 and 50 with cap to GND?

    Though it requires extra components, I would suggest the termination scheme below. This will reduce any DC-unbalancing that may occur. Can also result in not needing a common mode choke

    Alex LeBlanc said:
    Note that the daughter board's receiver needs an external termination resistor and 100nF capacitors:

    With the daughter board, I'm assuming the receiver needs to see a common mode voltage of ~1.2V. If so then move the capacitor to the left of the termination resistor and add the biasing scheme above. 

    Regards,

    Josh