Hi Team,
We are using DP83867CSRGZ in our design with SGMII Interface in between PHY and FPGA.
Please share the layout guidliness like below:-
1)Lenght Matching requirment
2)Skew in b/w P&N
3)Placement of AC coupling capactior
4)Do we need to keep Void or not beneath CAP
Many Thanks
Rajat
