We are designing MAC to communicate with the PHY chip DP83867IR/CR.
The datasheet is not clear on what interface we need to design to communicate with the RGMII interface on DP83867IR/CR. Is it CMOS or HSTL?
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We are designing MAC to communicate with the PHY chip DP83867IR/CR.
The datasheet is not clear on what interface we need to design to communicate with the RGMII interface on DP83867IR/CR. Is it CMOS or HSTL?
Hi Reza,
Our RGMII interface uses CMOS logic with signal going from 0 to VDDIO level. VDDIO can be 1.8,2.5, or 3.3V.
Best regards,
Melissa