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DS90UB954-Q1: DS90UB954 design review...

Part Number: DS90UB954-Q1


Hi Team,

Please help to check if there is any problem for customer design and input your comments.

Thanks.

954-3.pdf

  • Hello,

    Thank you for the schematic. I'll review the document and provide feedback by next Friday (10/20) at the latest.

    Regards,
    Darrah

  • Hello,

    Please find feedback listed below. Please note that comments on the AC coupling for RIN+/- and the decoupling capacitors on the power supply pins are an essential requirement for proper device behavior. If the proper capacitors and configuration is not used, the device will not behave as expected.

    • Pins 50-57: The 954 does not have pins 50-57. Are these meant to signify ground vias for the landing pattern?
    • Pins 4 and 5: See section 7.4.5 of the datasheet for a recommended crystals circuit. However if the current configuration comes from the chosen crystal's specific requirements provided by the manufacturer, continue to follow those instructions.
    • Pin 44: This is a reserved pin. The connection is not shown, but ensure that pin 44 is tied directly to ground.
    • Pin 6: BISTEN connection is not shown. Please note that when this pin is high the device will operate in BIST mode.
    • Pin 37: The mode voltage divider is not shown. Ensure that the mode pin voltage divider configuration follows the voltages from table 7-15 of the datasheet.
    • Pins 47 and 48: Pass and lock pin connection is not shown. Please note these are output only status pins.
    • Pin 30: PDB pin connection is not shown. Ensure that proper power sequencing is being followed. See section 9.2 of the datasheet for more details. Recommend either a software control method or a 10k pull-up resistor and a >10uF pulldown capacitor. See section 8.2 of the datasheet for an example.
    • Pin 35: Based on the comments it seems there is a desire to go between two IDX settings by populating and depopulating the resistors making up the voltage divider. This is okay, and if R262 is NC the 7 bit address will be 0x30, and if R263 is instead NC, the 7 bit address will be 0x3D. However, make sure that only one IDX configuration is being used at a time. Do not populate both R262 and R263 at the same time.
    • Pins 1 and 2: Recommend verifying that 4.7K is an appropriate pull-up resistance for the system's I2C bus capacitance.
    • Pins 1 and 2: 100nF capacitor is not necessary for I2C bus communication.
    • Since Pin 46 (VDD_SEL) is pulled high, the device will operate with an external 1.1V supply mode. Ensure that the 1.8V supply goes high before the 1.1V supply
    • There are various power supply pins with incorrect decoupling capacitors being used. Please see section 8.2 of the datasheet for proper decoupling capacitor values and placement. Since VDD_SEL is programming the device for external 1.1V mode, refer to figure 8-5 for proper VDD11 pin configuration.
    • The ferrite beads on the power supply pins require a DCR ≤ 25mΩ and Z = 120Ω@100MH
    • Pins 32, 33, 41, and 42: There does not appear to be any AC coupling or termination being done on the RIN0+/- or RIN1+/- pins. AC coupling and termination is required for proper operation of the device. Please see section 8.2.1 of the datasheet.
    • Pins 32, 33, 41, and 42: It is not very clear what is being done with the FRAKA connectors. Is there a PoC network in this system that is not being shown? The RIN+ and RIN- pins should not be connected together. Please see section 8.2 and 8.1.2