Other Parts Discussed in Thread: DP83869,
Hi team,
I'd like to use DP83869 for EtherCAT.
Which settings need to be changed for EtherCAT?
I'm trying to use TMDS64GPEVM for EtherCAT, but I am not able to link up.
BR.
Kengo.
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Hi Kengo,
Typically for Ethercat, we want our ethernet PHY to use RMII or MII for the MAC interface and 100Base-TX/100Base-FX, depending if you're using copper or fiber. Could you provide a block diagram of your setup? What is the TMDS64GPEVM connecting to, i.e. who is the link partner? Is the TMDS64GPEVM the ethercat master or an ethercat slave?
Regards,
Alvaro
Hi Alvaro,
Thank you for your reply.
I am connecting TMDS64 to each other.
However, the master side is connected to the CPU by RGMII and the slave side by MII.
I am using copper wire.
Is it not possible to communicate under these conditions with the default settings?
BR,
Kengo.
Hi Kengo,
They should be able to communicate. Do you have access to the DP83869's registers? If so could you send a register dump, 0x00-0x1F, from both the Master and Slave 869 PHYs from the two separate boards that are being connected.
Regards,
Alvaro
Hi Kengo,
MII is the preferred method due to its lower latency. Below I have a description for configuring MII, but I wanted to know if you managed to fix the communication issue. As mentioned before, the configuration you have should work. Please correct me if my understanding is wrong, but I believe you have:
TMDS64 Board #1 | Connector | TMDS64 Board #2 |
CPU <-RGMII-> 869 PHY | <- Ethernet Cable-> | 869 PHY <-MII-> CPU |
Configuring the DP83869HM into MII is a little tricky, please reference Section 1.9 MII-to-Copper in Understanding Different Modes of Operation in DP83869. The main point of that section is that Register access is required to set up MII in the DP83869HM. Register 0x01DF must be set to 0x0060. Please read the section for more details.
Note: Register 0x01DF is an Extended Register and cannot be written/read to directly, please see Extended Register Space Access for Ethernet PHYs
Regards,
Alvaro