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DS90UB948-Q1: OUTPUT_ENABLE and Digital reset

Shinji Tsuji
Genius 14119 points
Part Number: DS90UB948-Q1

Hi team,

It is recommended to assert Digital Reset (0x01[0]), when you toggle OUTPUT_ENABLE.

Is it mandatory? What is the purpose to reset after toggling OUTPUT_ENABLE?

If I assert digital reset, LOCK signal will go High --> Low --> High and I would like to avoid this LOCK pin glitch. 

Datasheet P59, Table 7-15, OUTPUT_ENABLE register description.

"Output Enable Override Value (in conjunction with Output Sleep
State Select)
If the Override control is not set, the Output Enable will be set to 1.
A Digital reset 0x01[0] should be asserted after toggling Output
Enable bit LOW to HIGH"

regards,

  • 0
    TI__Mastermind 21245 points

    Hello,

    Shinji Tsuji said:
    Is it mandatory? What is the purpose to reset after toggling OUTPUT_ENABLE?

    Yes, this is mandatory. Please see section 7.3.5 - Clock and Output Status of the DS90UB948 data sheet for more information.

    Shinji Tsuji said:
    If I assert digital reset, LOCK signal will go High --> Low --> High and I would like to avoid this LOCK pin glitch. 

    Please allow me until the end of this week to look into this issue.

    Best,

    Nikolas

  • 0
    TI__Mastermind 21245 points

    Hello again,

    It is possible for LOCK to potentially drop when performing a digital reset. To avoid this, you can configure the 948 so that LOCK is always high (with or without video) as long as LINK has been established. This can be done by setting 0x34[6] to 1.

    May I ask why you are attempting to override that bit? There may be a more efficient way to achieve what you are looking to accomplish.

    Best,

    Nikolas