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TCAN4550: Difference between buffers (regular, FIFO, queue)

Part Number: TCAN4550


I am trying to implement CAN using the TCAN4550, but I am not sure what kind of data buffers I need, because I don't know the difference between the mentioned terms.

What kind of buffers can be used in the TCAN4550? I read about a FIFO buffer, regular buffer and Queues, is that correct?

If so, what is the difference between the three of them? I get the functionality of FIFO buffers; first in first out. But how about the other two?

In the registers (and also in the example code) of the TCAN4550, I see the possibility to set FIFO or regular buffers in the MRAM, but not a queue.

How would one implement the usage of queues?

  • Hi Laura,

    The TCAN4550 uses the MCAN IP developed by Bosch, so I will refer you to the MCAN Users Manual as a reference for a deeper description of the MCAN features.  (Link)

    But I will try to briefly explain it as well.  You can configure up to 32 "Transmit Buffer Elements" that will store a message that should be transmitted on the CAN bus by setting the corresponding bit in the TX Buffer Add Request (TXBAR) register.  The allocation of these 32 buffers as a FIFO, Queue, or Dedicated Buffer comes down to your preference on how you want to transmit the messages and work with the CAN FD protocol message arbitration.

    A Dedicated TX Buffer is just what it sounds like, a dedicated buffer.  Once you write a message into the buffer and set the corresponding TXBAR bit, it will try to be transmitted.   If you have multiple message buffers and messages to transmit, you will need to manage the buffers and keep track of which buffer elements have been transmitted, and which ones are still pending.

    A FIFO or Queue can also be used which makes multiple message transmission easier to manage.  You can use either the FIFO or the Queue but not both at the same time.  You can however still have some dedicated TX Buffer elements in addition to either the FIFO or Queue buffers.

    A FIFO is as described, a First In First Out approach and the device will transmit the messages in the order they were placed in the FIFO regardless of the message ID.

    A Queue is similar to a FIFO, but the device will first compare the message ID value for all messages that are in the Queue and prioritize the transmission of the message with the lowest message ID based on the CAN FD Arbitration protocol.  This ensures that the highest priority message is always transmitted out of the queue first, unlike with the FIFO which transmits them in the order they were placed in the FIFO.

    Regards,

    Jonathan

  • Hello Jonathan,


    Thank you for your reply, it is very explanitory.

    Does that mean that if multiple messages were to be written to a TX Buffer, setting the TXBAR bit would result in one message being sent?

    Or is that the case in all forms of buffers? So that one send-request will always send one message, the only/main difference between the buffer types is the order in which messages in the buffer are being sent?

  • Hello Laura,

    Only one message can be written to a TX Buffer at a time.  If you want to use the same TX Buffer for multiple messages, you would have to write the first message to the TX Buffer and set the corresponding TX Buffer Add Request bit.  Then the device will set the corresponding bit in the TX Buffer Request Pending while the device tries to transmit the message.  Depending on the bus activity, and the message ID used for the Arbitration, the required to transmit a message may vary.  However, once the message has successfully been transmitted, the TX Buffer Request Pending bit will be de-asserted and the corresponding bit in the TX Buffer Request Transmission Occurred register will be set to indicate a successful transmission.  You can also enable device interrupts to relay this information to the MCU.

    Once the TX Buffer is available again, it can be reused for an additional message and the process would repeat.

    If you need to send multiple messages at a time, you would need to have multiple TX Buffers configured so that you can write all the messages to their own TX Buffer and then set the corresponding TX Buffer Address Request Bits for all messages you want to transmit.  The TCAN4550 will then try to transmit all messages using the same sequence of events as I've described for a single message.

    You can configure up to 32 TX Buffer Elements.  If they are all dedicated buffers, you can monitor the TX Buffer Request Pending register to determine which buffer elements are available and which ones still have messages pending transmission.  You can then determine where to store your next message for transmission.

    if you configure the TX buffers for either a FIFO or a Queue, you will need to monitor the TX FIFO/Queue Status register to determine which buffer elements are occupied and where to place your next message for transmission through the Put Index.

    You can also have a combination of dedicated buffers and the FIFO/Queue if you would like (but still only up to the 32 max).  An example of why you might want to have a dedicated buffer is if there is a specific message that is frequently sent that does not change value.  By storing it in a dedicated TX Buffer that you didn't overwrite, you simply resend the message without having to write it back into the buffer element through SPI every time you wanted to send it again.  You would simply need to set the TX Buffer Add Request bit for that buffer again to start a new transmission.

    Regards,

    Jonathan

  • Hello Jonathan,

    Thank you very much for this detailed explanation!
    Things have become much more clear! :)

  • Hello Laura,

    You are welcome.  Let us know if you have any additional questions.

    Regards,

    Jonathan

  • I am just now implementing the correct MRAM structure (before I was using the example code structure).

    So if I understand correctly:

    Separate Tx Buffers are the same as a Tx FIFO (with the same element size and count) in terms of MRAM allocation.
    The main difference between the two is that the Tx FIFO has a get-index and a put-index which helps the programmer determine in which buffer to put the data/read the data from.

    So in order to put a message on the CAN-bus using a Tx FIFO I have to read the put-index, and then write to that buffer, and set the transmit request-bit corresponding to that buffer?

  • Hi Laura,

    Separate Tx Buffers are the same as a Tx FIFO (with the same element size and count) in terms of MRAM allocation.
    The main difference between the two is that the Tx FIFO has a get-index and a put-index which helps the programmer determine in which buffer to put the data/read the data from.

    Correct. You can create up to 32 TX buffers and each buffer has a Buffer Index ID number (0-31) and a physical MRAM memory location.  The difference in the "Dedicated", "FIFO", and "Queue" terminology is simply how you want to manage which TX Buffers to use for your messages.  They all point to the same physical buffers in MRAM space. 

    You can configure all TX buffers to be Dedicated buffers where the MCU keeps track of the buffers and their transmission status. 

    Or you can have all TX buffers be either a FIFO or a Queue where the MCU must first read the Put Index value of the next available TX Buffer that should be used.

    Or you can have a mixture of both some dedicated TX Buffers and some FIFO/Queue TX Buffers.  In this configuration the dedicated TX Buffers have lower index numbers and the FIFO/Queue TX Buffers use the higher index numbers.

    To help illustrate the buffers, the MCAN User's Manual has the following figure.  If you only had a TX FIFO, then the TX FIFO would start at Buffer Index 0.

    So in order to put a message on the CAN-bus using a Tx FIFO I have to read the put-index, and then write to that buffer, and set the transmit request-bit corresponding to that buffer?

    Correct. 

    The process is always the same.  You first write the message to the TX Buffer, and then you set the corresponding bit in the TXBAR that correlates with the Buffer Index.  If you write messages to multiple TX Buffers, you will need to set the TXBAR bits for all buffers that contain new messages to send.

    When using a FIFO or a Queue, you just have to first read the Put Index so that you correctly place the message in the next available TX Buffer element the device wants you to use.

    Regards,

    Jonathan

  • Thank you very much! :)

  • You're welcome.  Let me know if you have any additional questions.

    Regards,

    Jonathan