TCAN4550-Q1: Consequences of ignoring clock optimization

Hello Peter,

First off the SPI baud rate is determined by the SPI clock created by the MCU and the TCAN4550 SPI interface is completely edge based, so there are no clock tolerance issues from a SPI frequency standpoint.

Also, just to make sure you understand my explanation, a "Transimpedance Amplifier" is just an amplifier that sources a current with respect to an input voltage.  Basically the amount of current it outputs or sources will vary as the voltage on it's input changes.  The TCAN4550 will try to adjust the amount of current it sources to the crystal based on the amplitude of the voltage in the oscillation waveform that it produces.  The "Transconductance" is just the change in current of the amplifier relative to this voltage or essentially the "gain" of the amplifier.

The TCAN4550 supports both a Crystal and a Single-Ended Clock source on the OSC1/OSC2 pins and the device uses a weak 1uA current source and a comparator on the OSC2 pin to check whether the OSC2 pin is "grounded" so that it knows which type of clock mode is used.  If at startup the device detects a voltage less than the comparator's reference voltage (typically 100mV but 150mV max) then it will disable the crystal's transimpedance amplifier and expect a single-ended clock to be supplied on the OSC1 pin.  But if the OSC2 pin voltage is greater than the threshold, the device will enable the crystal's transimpedance amplifier and source current out of the OSC1 pin to the crystal and then use the oscillation waveform on the OSC2 pin for the clock input.

The potential issue is not with optimizing the crystal for any type of frequency tolerance, but rather to ensure that the voltage waveform on the OSC2 pin does not drop below the comparator threshold used to detect a "grounded" pin. 

There is not a mechanism to disable the comparator after the device has started up and the clock mode selection has been made, so it is absolutely critical to maintain an OSC2 pin voltage greater than 150mV under all Process, Voltage, and Temperature operating conditions. Failure to do so can cause the device to switch to single-ended clock mode during normal operation and disable the transimpedance amplifier sourcing current to the crystal and instead expects a single-ended clock to be supplied on OSC1.  However, because there is NOT a single-ended clock signal on OSC1 that reaches the 0V to VIO amplitude requirements, the device will not have a clock to operate the digital core or MCAN controller.  The device will essentially be "paused" until the clock mode switches back to the crystal mode. 

During this time Any SPI and CAN communication that occurs during this clock outage will result in errors.

There is an automatic gain control circuit that will try to adjust the current to maintain appropriate oscillation levels with roughly an amplitude of 1Vpp and an common mode voltage around 700mV.  If the total external load from the crystal, capacitors, and any resistors between the OSC1 and OSC2 pins is not optimized, it is possible that the oscillation waveform amplitude can become greater than 1Vpp even though the automatic gain control circuit is sourcing current at the minimum level.  If this occurs, the TCAN4550 can't adjust the current any lower and reduce the amplitude Vpp.  Because the common mode voltage stays relatively stable, a larger Vpp amplitude results in higher "high peak" voltages  and lower "low peak" voltages on the waveform.  These lower peak voltages can become low enough to cause the single-ended detection comparator to trigger and switch modes.

When the device switches to single-ended mode, the transimpedance amplifier will stop sourcing current to the crystal and the oscillation amplitude will start to naturally decay through the parasitic losses in the circuit.  Once the Vpp amplitude becomes low enough to increase the OSC2 pin voltage above the threshold the device will switch back to crystal mode and current will again be supplied to the crystal.  The TCAN4550 will again have a clock, but the Vpp amplitude will again start to increase until the mode switch cycle repeats resulting in short periods of clock disruption in between segments of time that are working properly.

Component tolerance factors between the Transimpedance amplifier's transconductance, the crystal's motional parameters (internal equivalent capacitance, inductance, and resistance) and ESR value, the load capacitor tolerance factors, and the change in those values across temperature all need to be considered.  For example an increase in temperature can cause the PCB parasitic capacitance drop which changes the capacitive load on the crystal which will increase the Vpp amplitude.

The critical parameter is the Drive Level which is the power dissipation across the crystal.  Because crystals are mechanical elements, a larger power dissipation will result in a larger mechanical vibration and a larger induced voltage waveform.  In order to reduce the voltage amplitude, we need to reduce the drive level which is DL = Irms^2 * Rload.

There are two methods to reduce the DL.  The first is to reduce the current flowing through the crystal and this is done by adding a series Dampening Resistor between the OSC1 pin and the crystal which will reduce or restrict the current and "dampen" the oscillation Vpp voltage.

If a series resistor is not available, we can also reduce the Resistive Load (Rload) which is done by increasing the Load Capacitance which is in the Denominator of the Rload equation.  An increase in Cload results in a smaller Rload. 

When a series Rd resistor is used, typical values are between 30 and 100 ohms.  The exact value needed would have to be determined for your specific board.  This value should not be larger than necessary because it is directly subtracted from the "Negative Resistance" or the amount of extra margin available for the TCAN4550's amplifier to adjust to changes in the circuit due to component tolerance.  Having a Rd resistor that is too large can prevent the oscillation from starting or also place it at a risk of stopping.  Generally you want the negative resistance to be at least 3x to 5x the value of the Rload.

Increasing the Cload results in a small frequency shift, so this too would need to be verified that it doesn't cause other errors such as with the CAN bit timing and there is still enough tolerance to correctly send and receive the CAN messages.  However, typically there is enough tolerance allowed in CAN that there is no issue increasing the capacitor values to a level needed to prevent a clock mode switch.

The other concern is that if the Drive Level is not optimized and allowed to be too large, the crystal can have a large mechanical vibration which could cause mechanical stress on the crystal which could lead to reduced lifespan and eventual failure.  Crystal datasheets usually specify the minimum DL needed to sustain oscillations (such as 10uW) and also a maximum DL (such as either 100uW or 200uW which are common values).

Regards,

Jonathan

Jonathon,

You write that "with NX2016SA 40MHz crystal, I've seen stable operation with load caps between 8pF and 12pF, but the amount of PCB parasitic capacitance is different for all applications." Is this observation for circuits without the damping resistor?

--Peter

Hi Jonathan,

I have an oscilloscope and probe and am now exploring our circuit. The scope has a 1.5-GHz bandwidth and the probe is an active differential probe with 0.7-pF input capacitance and 200k input impedance (Keysight N2750A). This was my best guess at equipment that would allow me to make the necessary measurements.

I can measure the voltage across CL1 and across the crystal, by which I mean I get clean sine waves with amplitudes on the 100-mV scale and with frequencies of 40 MHz. However, when I probe CL2, the oscillations stop. My plan was to measure CL2 to ensure the minimum voltage stayed well above the 150-mV threshold. Am I mistaken that I can measure this directly? Can I learn anything from fact that probing CL2 kills the oscillation? (At the moment, I am testing our current board, which has 33-pF caps for CL1 and CL2.)

--Peter

Hi Peter,

The scope and probe specs should be ok for this testing.  My first thoughts are that there is an upper limit to how much capacitance that can be tolerated, so with 33-pF caps, the additional scope probe might be pushing the circuit over the limit.

Can you make measurements on CL2 that do not stall the oscillations when the cap values are smaller?

Do you have the ability to monitor the GPIO pin with a scope probe?

When you say that you see sine waves with amplitudes on the 100-mV scale (for CL1) are you saying the peak-to-peak amplitude of that sine wave is only 100-mV?  Typically the amplitude would be roughly 1-Vpp.

Perhaps there is a misunderstanding with what the 100-mV is referring too.  We need to simply ensure that the complete waveform on the OSC2 pin remains above the 150-mV level with respect to GND.  The typical Vpp is closer to 1-V with a common mode voltage around 700-mV.

What are your Vpp and Vcm levels for the sine waves you are measuring?

Regards,

Jonathan

Jonathan,

I think I understand the goal, to ensure the minimum value of the wiggle at OSC2 over time is always well above 150 mV. Or to put it mathematically, ensure that min[Vpp/2*sin(w*t) + Vcm] > 150 mV. And I think the differential voltage across CL2 is equivalent to the single-ended voltage of OCS2 to ground.

Across CL1, my measurements for Vpp and Vcm are 700 mV and 890 mV, resp.

Across the crystal, my measurements for Vpp and Vcm are 705 mV and 885 mV, resp.

I could find a way to probe the GPIO pin, yes.

--Peter

Peter,

Yes, you understand the goal.  We recommend trying to maintain at least an additional 100-mV of margin to the maximum single-ended comparator's detection threshold of 150-mV just to account for statistical variation, and other operating effects such as capacitor de-rating over time, etc.  This would mean our target is to maintain  an OSC2 waveform greater than 250mV.

I will also note that the Automatic Gain Control circuit is sensing the OSC1 waveform for the Vpp level and adjusts the output current of the of the amplifier to try and maintain a 1-Vpp amplitude.  Generally with to little capacitance, we can see that the amplitude exceed 1-Vpp, even when the AGC has reduced the current to the minimum value.  In this situation, the TCAN4550 is not capable of controlling and preventing the Vpp voltage from crossing the single-ended detection threshold and prevent an unwanted mode change.

When there is too much capacitance, the Vpp level may not reach a full 1-Vpp amplitude even when the AGC is outputting the maximum current.  This reduces the negative resistance and safety factor and can cause the oscillations to stop.  This is likely what you are seeing with 33-pF capacitors which sound too large to me based on my general experience with this device.  So we don't want to overload the circuit either.

One additional observation we've made is that it is possible to increase the Vcm levels on the OSC2 side of the crystal by shifting the amount of capacitance to be more on the OSC2 side and less on the OSC1 side.  The overall amount of combined capacitance due to the sum of the two caps can remain the same.  But this technique can add a bit more voltage margin if needed.

It is possible to enter a clock test mode to mux out a divided down version of the internal clock on the GPIO1 pin.  This prevents the device from operating in other ways and CAN communication is not possible.  But it can be useful to see if the clock is stable while sweeping environmental conditions such as temperature without having to connect a scope probe directly to crystal which adds additional loading and can skew the results.  If this is of interest to you, I can email you the SPI register configuration offline to the email you used to register with E2E.

Regards,

Jonathan

Yes, please send the configuration offline.

I have sent you some information through email.  Let me know if you have any questions.

Regards,

Jonathan