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SN75LVDT1422: Failure modes of the SN75LVDT1422 associated with setup/hold violations

Curtis Mulady
Prodigy 50 points
Part Number: SN75LVDT1422

For this question, I am specifically referring to setup/hold violations associated with the TA[6:0] and TB[6:0] pins (parallel inputs).

I have an application that uses a bank of SN75LVDT1422 devices to transmit data from a parallel bus to an FPGA. Some of the bits on that bus are asynchronous to any clocks in the system, thus violations of the SN75LVDT1422 setup/hold times on the TA[n]/TB[n] pins are inevitable. Does Texas Instruments have any literature or information on the failure modes of the SN75LVDT1422 when these violations occur?

One obvious failure mode is that the bit in the serial stream associated with the TA[n]/TB[n] pin that violated the timing spec would be in the "incorrect" state. This failure mode is not a problem in our application.

Are there any other failure modes, such as "corruption of adjacent bits", lockup, or "serial transmitter timing violations"?

  • 0
    TI__Guru**** 176971 points

    Hi,

    The SN75LVDT1422 loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices.

    But the SN75LVDT1422 does not check the data bits that are being received, so if the input setup/hold timing is violated, it will clock out the wrong serial data at the output.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 50 points

    Understood. Does TI have any details on precisely how the device might "... clock out the wrong serial data at the output"?

    One of the concerns that I am really trying to chase down is this: Can adjacent bits in the serial stream be corrupted? E.g., if a waveform coming into TA[1] violates setup/hold, would only the second bit out of the TA+/- serial buffer be invalid, or is it possible for *other* bits in that stream to also be corrupted?

    Thanks,

    - Curtis Mulady

  • +1 in reply to Curtis Mulady
    TI__Guru**** 176971 points

    Curtis

    If a waveform coming into TA[1] violates setup/hold timing spec, then only this bit will not be clocked out correctly, but will not corrupt the adjacent bits.

    Thanks

    David