TCAN4550 SPI don't respone 0x41 read cmd ?

M3 SPI(Master)<------>TCAN4550 EVM(Slave)

Hi Nicolas,

Is your chip select (nCS) pin connected directly to GND? 

The TCAN4550 requires the nCS pin transition from a High to a Low at the start of a SPI transaction and then transition back to High at the end.  It counts the number of SPI Clock pulses between the these transactions to determine if there is the correct number of bits for the transaction and set a SPI error if it is incorrect.

Regards,

Jonathan

Thank u.

Where can you see that the nCS pin transition from a High to a Low at the start of a SPI transaction and then transition back to High at the end ？

Hi Nicolas,

In the signal plots you provided it says the nCS pin is connected to GND, and I do not see a transition of the signal at the beginning and end of your SPI transactions.  If nCS is connected to GND, then this is a problem because nCS must transition at the beginning and end of each SPI transaction to mark the begging and end of the transaction.

The Programming section of the datasheet shows the required signal format.  The Clocking diagram shows the transitions, although it is not labeled as nCS because this diagram is focused on the clock edges used with the SDI and SDO data.

The Write and Read diagrams also shows the nCS transitioning Low at the beginning and remaining Low until the end where it transitions High again.

Can you verify using your scope that the nCS is transitioning high to low in accordance with these diagrams?  Your plots don't have nCS connected, so perhaps can you connect CH3 to nCS and verify the SPI signals match the datasheet figures?

Regards,

Jonathan