DS90CF384: Sample the 24-Bit TTL Data at the Rising Edge of the Clock or Falling Edge of the RXCLKOUT (Pin#26)

Hello Nikolas,

Please check the waveforms which we are seeing at the output of the DS90CF384MTD/NOPB TSSOP-56.

Currently, the Data Transition (24-Bit R, G, B) on Channel#3 is happening on the Rising Edge of Clock (Channel#2), as shown in below waveform.

Please let us know if this can be changed to Falling Edge of clock.

Regards,

Tanveer Ahmed

Hello again,

I will look into this matter with my team and get back to you within three to five business days. 

Best,

Nikolas

Hello Tanveer,

To the best of my knowledge, to change the transmitter to the falling edge of the clock, it must be adjusted from the receiver side of the system. The data sheet states, "A rising edge transmitter will inter-operate with a falling edge receiver without any translation logic." Strobe select can be found on pin 17 (R_FB) of the receiver (DS90C383).

Best,

Nikolas

Hello Nikolas,

Below is the block diagram of my schematics.

Here, LVDS Channel A (Channel 0) of iMX6 Apalis SoM/CoM Module is connected to the TI IC for LVDS to 24-Bit RGB TTL Conversion.

How can we change the Clock from Positive Edge Triggered to Negative Edge Triggered (or vice-versa)?

Hi Nikolas,

Thank you for the reply. One more query regarding your comment "the clock strobe will have to be toggled directly from your SoC".

Does it mean I need to change the LVDS Clock Polarity from the SoM Side (CLK+ to CLK- and vice-versa)?

Kindly let me know this.

Regards,

Tanveer Ahmed