Hello TI Team,
- TPS27081ADDCR,
- TPS3808G18DBVT,
- SN65HVD70D
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Hello TI Team,
Hi Sonali,
So for the SN65HVD70D portion of the schematic I only have one note - the /RE and D pins should have a default state so that it never is left floating. If the M40_GPIO0_00 and UART4_TX signals are always defined during operation the risk is minimal - but you do not want to leave any logic input pin floating during operation as it can cause issues such as increase power consumption and noise generation.
I will loop in our power team to look at the other 2 devices on your list as they are going to be better suited to help you on that portion of the schematic.
Best,
Parker Dodson
Thanks Parker,
Hi Sonali,
TPS27081ADDCR schematic looks good.
TPS3808G18DBVT looks ok with the exception that R59 should be populated as the RST output is open drain. I will assign this to the voltage supervisor/watchdog team in case they have further comments.
Thanks,
Patrick
Hello Parker,
Thank you for your feedback.
Also, in the datasheet, they mentioned DE has an internal pull-down resistor and D has an internal pull-up resistor. Still, do we need to add an external default state for these pins?
If yes, could you please suggest to us which default state (pull-up or pull-down) should we provide to /RE, DE, and D signals?
Thanks,
Sonali
Hi Sonali,
I am so sorry for the delay here - I missed the notification - I apologize for that.
So there are weak biasing resistors (1MEG) on those pins - so you don't need the external resistors - I apologize we usually indicate pull-ups/pull-downs more clearly in the datasheet and not in the eq. circuits so it looks like I was mistaken so the schematic is okay for the SN65HVD70 Device.
Best,
Parker Dodson
Hello Parker,
Thank you for your feedback.
As there is no internal pull-up/pull-down resistor on /RE pin. I have added the external pull-up on /RE pin.
Thanks,
Sonali
Sonali,
What is the issue - you said you implemented a external pull-up on /RE.
You didn't ask another question - there is no update.
Best,
Parker