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TUSB8042A: GRSTz Implementation

Jonathan Mi
Prodigy 40 points
Part Number: TUSB8042A

Hello,

I am currently designing carrier board for Orin NX with TUSB8042A for USB SS hub. 

Please correct me if my understanding is wrong.

For power sequencing requirements, VDD33 and VDD can have any sequence, as long as GRSTz is held low until at least 3ms after both VDD33 and VDD are stable.

This seems to match the way the EVM is designed, with 1.1V supply chained off of 3.3V supply, and a 1uF capacitor to ground that charges to 2V (VIH, min) in > 3ms. When power is supplied, GRSTz starts low, and then is charged through the PU resistor until GRSTz is high, enabling the controller.

However, my confusion is that the second half of note 1 in timing requirements section states that if only a capacitor is connected from GRSTz to GND, then an external signal is required to trigger GRSTz. This is in conflict with the first half of the statement and in conflict with how the EVM is designed.

Furthermore, the language for GRSTz is very confusing. The pin description states that if GRSTz is asserted, then the IC is disabled. But GRSTz is active low, which means that normal operation should have GRST_N asserted, which means GRST is low.

Please advise, thank you.

  • 0
    TI__Guru** 120065 points

    Jonathan:

     your understanding is correct for 

    "For power sequencing requirements, VDD33 and VDD can have any sequence, as long as GRSTz is held low until at least 3ms after both VDD33 and VDD are stable."

    for GRSTz, z means active low ( in reset mode), When GRSTz is high, device is in normal working mode.

    Regards

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 40 points

    What about the second part of note 1 in timing requirements? From your response and the EVM it appears that proper function can be achieved by connecting only an properly sized capacitor from GRSTz to GND, and the system is agnostic to whether VDD or VDD33 is stable first. (Eg: VDD33 can be stable before VDD)

    For reference, this is note 1: "If GRSTz is only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33."

  • 0 in reply to Jonathan Mi
    TI__Guru** 120065 points

    For this note: "If GRSTz is only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33."

      Since GRSTz will follow VDD33, if VDD come up late than VDD33. It could happen that VDD is not stable yet but GRSTz already goes high, then hub device may not get enough time for reset.

    Regards

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 40 points

    Right, but with an appropriately sized capacitor, GRSTz can be designed to go high at least 3ms after VDD is stable? 

    For example, with a 1uF capacitor and looking at the minimum value of RPU (14.5kOhm), it takes 13.51ms for GRSTz to rise from 0V to 2V (VIH, min). Then as long as VDD is stable <~9ms after VDD33 is stable (let's say it takes <1ms for VDD33 to be stable), the timing requirements can be met?

  • +1 in reply to Jonathan Mi
    TI__Guru** 120065 points

    Hi:

    There are two .conditions here:

    1; if you can control GRSTz, there is no power on sequence  as long as GRSTz goes high 3ms after VDD is stable.

    2; if you can't control GRSTz externally and just use external capacitor on GRSTz, then  VDD should up 10us before VDD33. You don't need to meet 3ms here. We suggest 1uf to start with.

    Regards

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 40 points

    OK, I will just try with appropriately sized capacitor first and include option for external control signal if external capacitor does not work. Thanks.