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Inverted Gate MOSFET



Hello Dears,

I am working on an new design with discrette MOSFETs and I do not know where Ido I find discrette Mosfet whit an inverting Gate. See on this schematic. I am looking for only upper transistor as discrette component. Do you know any concrettely types?

  • Hello Ivan,

    Thanks for the inquiry. You may be able to use a P-channel FET for the upper device with the source connected to Vdd. To turn the device on, pull the gate pin low and to turn it off, pull the gate pin up to Vdd. TI has a portfolio of P-channel FETs that can be found at the link below. Please review and let me know if you have any questions.

    https://www.ti.com/power-management/mosfets/p-channel-transistors/products.html

    Best Regards,

    John Wallace

    TI FET Applications

  • Hello John,

    thanks for your message. If I understand about upper schematic diagram, both MOSFETS turn on If all Gats are connected to V+. It means, the upper MOSFET is P-channel with inverted gate. That means I need P-channel MOSFET when it is drived by V+ on gate. It is not standard P-channel mosfet. But maybe is probably, that I does not understand the idea of the scheme. Because this would mean that both mosfets would turn on at the same time, thus shorting the power supply. And I need that. My alternative schematics diagram is:


    I think that P-channel with inverting gate is not in your link.

  • An N-channel MOSFET turns on when the gate voltage is sufficiently above the source voltage.
    A P-channel MOSFET turns on when the gate voltage is sufficiently below the source voltage.

    In the circuit in your question, the sources are connected to Vss and Vdd; both drains are connected to Q. Only one MOSFET will be active at the same time.

  • Hello Ivan and Thanks Clemens,

    In your original circuit diagram, the upper MOSFET is the P-channel device and the lower MOSFET is the N-channel. The source of the PFET is connected to VDD and it's drain is connected to Q. The drain of the NFET is connected to Q and its source is connected to VSS. The gates are tied together and the logic signal A should switch between VDD (NFET on, PFET off, Q pulled low to VSS) and VSS (NFET off, PFET on, Q pulled high to VDD). Please let me know if you have additional questions.

    Thanks,

    John