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DS280DF810: Could not read the correct value of CTLE

Shengyue Zhong
Intellectual 1340 points
Part Number: DS280DF810


Hi Team,

One of my customers is using DS280DF810, it's a 28.2Gbps application, they found in some operating conditions the packets loss will occur. Customer suspect that the loss in the link is quite large, currently, they are using DFE and CTLE adaptive mode3, there are still channels with packet loss. After setting, we can get the DFE value from 0x71 to 0x75. but the value of CTLE always reads 0 (both in mode2 and mode3), does that mean that they are not using CTLE correctly? In addition to configuring the adaptive mode enable, could you please check Register settings below and share the advice what else should they do with the CTLE?

Thanks.

CDR_REG.xlsx

  • 0
    TI__Mastermind 29870 points

    Hi,

    I have some questions for the customer.

    1. When you say packet loss is occurring, does this mean you are seeing a large number of bit errors?
    2. I believe there may be a mistake with your manual data rate register settings. For 28.2 Gbps, Register 0x61 and 0x63 should be set to 0x46, not 0xc6. Can you try making this change and see if this resolves the issue?
    3. Have you measured an eye diagram of the retimer output? If so, can you share it with me?
    4. It's possible the CTLE is adapting to 0 intentionally if this is a low loss application. Do you have a measure of the insertion loss on the channel receiver?
    5. Can you try setting adapt mode 1 and see if the CTLE value in register 0x8F is nonzero?

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Intellectual 1340 points

    Hi Lucas,

    please find answers below.

    1. Customer could only see packet loss, could not verify if bit errors exist.

    2. If register 0x61 and 0x63 set to 0x46, all channels will not work because of speed setting does not match. if they use register settings according with the excel, channels could work besides packet loss occurs in some channels.

    3. The eye diagram doesn't show anything weird.

    4. The insertion loss could not be measured.

    5. 0x8F is still zero in mode 1.

  • 0 in reply to Shengyue Zhong
    TI__Mastermind 29870 points

    Hi Shengyue,

    Shengyue Zhong said:
    2. If register 0x61 and 0x63 set to 0x46, all channels will not work because of speed setting does not match. if they use register settings according with the excel, channels could work besides packet loss occurs in some channels.

    My mistake, I missed that bit 7 is an override enable. The customer's rate setting values are correct.

    Shengyue Zhong said:
    4. The insertion loss could not be measured.

    Is the customer using the retimer on a PCB? If so, I can estimate the insertion loss based on a few parameters.

    • What is the PCB material used?
    • What is the trace length of retimer CML inputs?
    • Are there connectors on these traces? If so, how many?

    Does the customer have a configuration script they can share? If they do, it would be helpful for me to see exactly which register values they are setting.

    I have a few additional ideas the customer can try.

    1. Did you intentionally set register 0x13[2]=1? This configures the final stage of the equalizer to be a limiting stage. Can you try setting this bit to 0 and resetting the CDR (write reg 0xA=0xC, then 0xA=0x0) to see if this changes anything?
    2. I noticed register 0x95[3] is 0 when the default value should be 1. Can you try setting this bit to 1 and resetting the CDR to see if this changes anything?

    Best,

    Lucas