DP83869HM: Good approch For clock distribution between 3 PHY chip.

Hello,

We are working on TSN complient device and we have 3x DP83869HM, my Question is What is the good approch to Distribute 25MHz clock?

1) Using Clock buffer and Distribute clock to all three PHY or 

2) Using Ethernet PHY CLK_OUT. (25MHz Clock --> PHY1 XI,   PHY1 PHY CLK_OUT --> PHY2 XI,   PHY2 PHY CLK_OUT --> PHY3 XI)

Regards,

Punit Patel