Hello,
I'd like to first follow up with the undocumented clock divider settings in this forum. Are there any plans to add to this to the datasheet? Or were they added elsewhere?
Secondly, I'm having issues getting a camera stream using a DS90UB954 and DS90UB953 pair and an NVIDIA Jetson Orin NX. I have an open forum thread with NVIDIA to debug that side in conjunction with this.
Right now I am using the pattern generation feature on the deserializer to try to isolate issues. You can see the forum post I mentioned above here, NVIDIA forum, which includes my pattern gen settings.
I used the TI forum linked above to set the lowest CSI-TX setting of 1.3 Gbps to avoid needing to do skew calibration on the Des / SoC. I see in section 7.4.21 in the datasheet, it says:
"In the case of alternate settings, the respective CSI-2 timing parameters registers must be programmed, and the appropriate override bit must be set. For the 1.664-Gbps and 1.472-Gbps options, these settings will also affect internal device timing for back channel operation, I2C, Bidirectional Control Channel, and FrameSync operation which scale with the REFCLK frequency."
I assume I am in the "case of alternate settings" but I am confused on how exactly the internal device timing is affected. What changes do these require / what should I be on the lookout for? I think I also need to change registers 0x40 to 0x48 on indirect access page 0 but I am also unsure of how to modify these or what to set them too.
For our use case, we are using a Sony IMX219 camera sensor (datasheet) in 2 lane configuration. The data rate is 912 Mbps per lane. I set the Des to be 1.3 Gbps since it is the closest option to the default 800 Mbps per lane. Will this work? Do the input and output data rates need to match?
Thank you!
