• State Resolved
  • Locked Locked
  • Replies 15 replies
  • Answers 4 answers
  • Subscribers 33 subscribers
  • Views 742 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DS90UB949A-Q1: Writing custom EDID content to internal pre programed SRAM

DS90UB949A-Q1: Interface forum

Bruce Deng
Prodigy 90 points
Part Number: DS90UB949A-Q1
Other Parts Discussed in Thread: ALP

Hello,

I have a HDMI source -> 949 -> 948 -> 1080p display.

I am trying to keep the HDMI source plugged into the 949 at all times, including through power cycle. However, this results in the display using the wrong EDID and displaying the wrong image. The image can only be resolved correctly by unplugging and replugging the HDMI. 

I am using the 949 eval board. I have tried moving switch 5 of MODE_1 high to strap EXT_CTL high on power up. However, this is not working, and the HDMI still connects and displays the wrong image. Furthermore, reading register 0x54 results in value 0x00, rather than the expected 0x80.

Is there a step I am missing to prevent HDMI from connecting before the EDID is loaded? 

  • 0
    TI__Mastermind 22946 points

    Hi Bruce,

    To clarify, which options for EDID information to the HDMI source are you supposed to use as below? Also what number of MODE_SEL0 is selected?

    1. Internal pre-programmed EDID
    2. Internal EDID loaded into device memory
    3. External local EDID (EEPROM)
    4. External remote EDID

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 90 points

    Hello,

    I am using an external remote EDID, loaded through I2C. 

    MODE_SEL0 is selected on switch 1. 

  • 0 in reply to Bruce Deng
    TI__Mastermind 22946 points

    Hi Bruce,

    In this mode, to load external EDID from the EEPROM at the remote display set the Serializers MODE_SEL0 to 1. For MODE_SEL1, REM_EDID_LOAD = 1 and EXT_CTL = 1 must be set as well. Note that remote EDID access might affect the display system, so you might need to know that once the Deserializer is powered on, i.e. PDB is enabled, the Serializer will access the Deserializer's local I2C bus within less than 1ms, looking for the address 0xA0 (8-bit address).

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 90 points

    Can you explain further what the impact of the PDB enable is? 

    I am trying to load an EDID via an MCU and I2C. Is it possible to disable the HDMI link on the 949 until the correct EDID is loaded such that I don't obtain an incorrect image on the display?

  • 0 in reply to Bruce Deng
    TI__Mastermind 22946 points

    Hi Bruce,

    Could you try to delay the init B until after the HDMI clock has become stable from the HDMI source for this to work properly? Please refer to the screenshots of the datasheet below for the sequence between PDB, HDMI, and I2C local and setting registers for the configuration. If it is still doesn't work, please share the desired PCLK of the image resolution & frame rate, the incorrect image phenomenon, and the reg dump.

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 90 points

    Hello, 

    Delaying init B did not work to resolve the issue. I've been using ALP to try to resolve this issue. We found that unchecking the box "Disable Auto HDCP" and then clicking "Deassert Hot-Plug" resolved the issue. However, I cannot find the register control for these two settings. Can you please advise how to change these two settings through I2C and register access?

  • 0 in reply to Bruce Deng
    TI__Mastermind 22946 points

    Hi Bruce, 

    To clarify, are you using UB949A or UH949A? In UH949A datasheet, 0x54 [3] indicates Automatic HDCP_CTRL setting. 

    Please refer to this E2E thread regarding Implementation of "De-assert Hot Plug". (Link) Note that s.HOT_PLUG_NOT = 0x01000000

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 90 points

    Hello,

    I am using the UB949, 0x54[3] on its datasheet is reserved. Thank you

  • 0 in reply to Bruce Deng
    Prodigy 90 points
    Josh Baik said:
    Note that s.HOT_PLUG_NOT = 0x01000000

    To confirm, the I2C register write commands would be:

    #Assert HPD
    # Select HDMI APB interface.
    board.WriteI2C(UB0949, 0x48, 0x01)
    board.WriteI2C(UB0949, 0x49, 0x00)
    board.WriteI2C(UB0949, 0x4A, 0x00)


    board.WriteI2C(UB0949, 0x4B, 0x01)
    board.WriteI2C(UB0949, 0x4C, 0x00)
    board.WriteI2C(UB0949, 0x4D, 0x00)
    board.WriteI2C(UB0949, 0x4E, 0x00)

    And the API looks like this?

    s.HDMI_SETUP_CTRL = 0x0000; # HDMI Setup Ctl Reg
    s.HOT_PLUG_NOT = 0x01000000; # Assert Hot plug not detected

    If I wanted to de-assert then assert the hot plug, do I need to delay between the two commands? For example:

    s.HDMI_SETUP_CTRL = 0x0000; # HDMI Setup Ctl Reg
    s.HOT_PLUG_NOT = 0x01000000; # Assert Hot plug not detected

    DELAY(xxx time)   ### Does xxx time need to be > 0? ###

    s.HDMI_SETUP_CTRL = 0x0000; # HDMI Setup Ctl Reg
    s.HOT_PLUG_DETECT = 0x01000001; # Assert Hot plug not detected

  • 0 in reply to Bruce Deng
    TI__Mastermind 22946 points

    Hi Bruce,

    I have updated the above comment for the link. The UB version doesn't support HDCP which is why it's reserved in the UB949 datasheet.

    Best,

    Josh

  • 0 in reply to Bruce Deng
    Prodigy 90 points

    Hi,

    Can I have a confirmation of the I2C commands for hot plug detect?

  • 0 in reply to Bruce Deng
    TI__Mastermind 22946 points

    Hi Bruce,

    It's correct. I would suggest delay between pulling the HPD low and pulling it high again, that way the host has enough time to know HPD dropped. Please refer to this E2E thread regarding HPD delay as more steps may be needed: (Link)

    Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 90 points

    Thank you for confirming The link does not appear to be working, could you re-link the new thread?

  • +1 in reply to Bruce Deng
    TI__Mastermind 22946 points

    Hi Bruce,

    Sorry, it was posted internally. I have copied the response.

    Please see if it works with the following steps:

    - Before the switchover is going to be made, manually pull the HPD low using the following config for 949:

    0x48 = 0x01
    0x49 = 0x00
    0x4A = 0x00
    0x4B = 0x01
    0x4C = 0x00
    0x4D = 0x00
    0x4E = 0x00

    - At this point, switch the HDMI mux to the other source 

    - After the switch has completed, issue a digital reset without registers to 949 by setting 0x01 = 0x01

    - Re-enable the HPD signal from 949:

    0x48 = 0x01
    0x49 = 0x00
    0x4A = 0x00
    0x4B = 0x01
    0x4C = 0x00
    0x4D = 0x00
    0x4E = 0x01

    - Now the HDMI source should recognize and go through the normal process to start the display 

    - After the HDMI source has started and the remote deserializer has locked to that input with the new clock rate, issue a digital reset to the deserializer by setting the deserializer 0x01 = 0x01 to ensure that the AEQ is starting from the lowest level which makes the process deterministic.

    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    There is another recommendation as long as you go through a HPD cycle and the HDMI interface re-inits, you shouldn't need to do a full reset of the 949, but it would be best to follow the steps in the 949 datasheet to issue commands after the TMDS clock stabilizes:

    - Before the switchover is going to be made, manually pull the HPD low using the following config for 949:

    0x48 = 0x01
    0x49 = 0x00
    0x4A = 0x00
    0x4B = 0x01
    0x4C = 0x00
    0x4D = 0x00
    0x4E = 0x00

    - At this point, switch the HDMI mux to the other source

    - Re-enable the HPD signal from 949:

    0x48 = 0x01
    0x49 = 0x00
    0x4A = 0x00
    0x4B = 0x01
    0x4C = 0x00
    0x4D = 0x00
    0x4E = 0x01

    -Wait until the new TMDS clock is stable from the HDMI source

    -Reset the HDMI PLL by writing the following registers:

    0x40 = 0x10
    0x41 = 0x49
    0x42 = 0x10
    0x42 = 0x00

    -Reset the FPD PLL by writing the following registers:

    0x40 = 0x14
    0x41 = 0x49
    0x42 = 0x10
    0x42 = 0x00

    -Reset the 948 by issuing 0x01 = 0x01 through the FPD-Link BCC

    You don't need to do anything with 0x48-0x4E after this process until you want to switch the source again

     Best,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 90 points

    That solved my issue, thanks for the help!